DRA790 Datasheet, PDF (368/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important
that the following recommendations are adopted in placing capacitors on the PDN.
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and
resistance. This was shown earlier in Figure 7-1. The capacitor mounting inductance and resistance
values include the inductance and resistance of the pads, trace, and vias. Whenever possible, use
footprints that have the lowest inductance configuration as shown in Figure 7-9
The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or
doubling the number of vias as shown in Figure 7-9. If the PCB manufacturing processes allow it and if
cost-effective, via-in-pad (VIP) geometries are strongly recommended.
In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z
is due to PCB thickness (as shown in Figure 7-9).
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in Figure 7-
9 are known as:
• 2-via, Skinny End Exit (2vSEE)
• 2-via, Wide End Exit (2vWEE)
• 2-via, Wide Side Exit (2vWSE)
• 4-via, Wide Side Exit (4vWSE)
• 2-via, In-Pad (2vIP)
Via
Pad
Via-in-pad
Trace
Mounting geometry for reduced inductance
SPRS906_PCB_FREQ_04
Figure 7-9. Capacitor Placement Geometry for Improved Mounting Inductance
NOTE
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was
used in place of 2vSEE.
Decoupling Capacitor (Dcap) Strategy:
368 Applications, Implementation, and Layout
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