DRA790 Datasheet, PDF (82/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
4.3.12 QSPI
NOTE
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the device TRM.
SIGNAL NAME
qspi1_sclk
qspi1_rtclk
qspi1_d0
qspi1_d1
qspi1_d2
qspi1_d3
qspi1_cs0
qspi1_cs1
qspi1_cs2
qspi1_cs3
Table 4-13. QSPI Signal Descriptions
DESCRIPTION
QSPI1 Serial Clock
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
QSPI1 Data[1]. Input read data in all modes.
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes.
QSPI1 Chip Select[1]
QSPI1 Chip Select[2]
QSPI1 Chip Select[3]
TYPE
IO
I
IO
IO
IO
IO
IO
O
O
O
4.3.13 McASP
BALL
F2
H3
K5
G2
K6
H4
G4
G3
L1
K3
NOTE
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (McASP) section of the device TRM.
Table 4-14. McASP Signal Descriptions
SIGNAL NAME DESCRIPTION
Multichannel Audio Serial Port 1
mcasp1_axr0
McASP1 Transmit/Receive Data
mcasp1_axr1
McASP1 Transmit/Receive Data
mcasp1_axr2
McASP1 Transmit/Receive Data
mcasp1_axr3
McASP1 Transmit/Receive Data
mcasp1_axr4
McASP1 Transmit/Receive Data
mcasp1_axr5
McASP1 Transmit/Receive Data
mcasp1_axr6
McASP1 Transmit/Receive Data
mcasp1_axr7
McASP1 Transmit/Receive Data
mcasp1_axr8
McASP1 Transmit/Receive Data
mcasp1_axr9
McASP1 Transmit/Receive Data
mcasp1_axr10 McASP1 Transmit/Receive Data
mcasp1_axr11 McASP1 Transmit/Receive Data
mcasp1_axr12 McASP1 Transmit/Receive Data
mcasp1_axr13 McASP1 Transmit/Receive Data
mcasp1_axr14 McASP1 Transmit/Receive Data
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
D14
B14
C14
B15
A15, J25
A14, J24
A17, H24
A16, H25
A18, H21
B17, K22
B16, K23
B18
A19
E17
E16
82
Terminal Configuration and Functions
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