DRA790 Datasheet, PDF (330/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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• Instruction packing
– Gives code size equivalence for eight instructions executed serially or in parallel
– Reduces code size, program fetches, and power consumption
• Conditional execution of most instructions
– Reduces costly branching
– Increases parallelism for higher sustained performance
• Efficient code execution on independent functional units
– Industry's most efficient C compiler on DSP benchmark suite
– Industry's first assembly optimizer for fast development and improved parallelization
• 8-/16-/32-bit/64-bit data support, providing efficient memory support for a variety of applications
• 40-bit arithmetic options which add extra precision for vocoders and other computationally intensive
applications
• Saturation and normalization to provide support for key arithmetic operations
• Field manipulation and instruction extract, set, clear, and bit counting support common operation found
in control and data manipulation applications.
The C66x CPU has the following additional features:
• Each multiplier can perform two 16 × 16-bit or four 8 × 8 bit multiplies every clock cycle.
• Quad 8-bit and dual 16-bit instruction set extensions with data flow support
• Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses
• Special communication-specific instructions have been added to address common operations in error-
correcting codes.
• Bit count and rotate hardware extends support for bit-level algorithms.
• Compact instructions: Common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce
code size.
• Protected mode operation: A two-level system of privileged program execution to support higher-
capability operating systems and system features such as memory protection.
• Exceptions support for error detection and program redirection to provide robust code execution
• Hardware support for modulo loop operation to reduce code size and allow interrupts during fully-
pipelined code
• Each multiplier can perform 32 × 32 bit multiplies
• Additional instructions to support complex multiplies allowing up to eight 16-bit multiply/add/subtracts
per clock cycle
The TMS320C66x has the following key improvements to the ISA:
• 4x Multiply Accumulate improvement for both fixed and floating point
• Improvement of the floating point arithmetic
• Enhancement of the vector processing capability for fixed and floating point
• Addition of domain-specific instructions for complex arithmetic and matrix operations
On the C66x ISA, the vector processing capability is improved by extending the width of the SIMD
instructions. The C674x DSP supports 2-way SIMD operations for 16-bit data and 4-way SIMD
operations for 8-bit data. C66x enhances this capabilities with the addition of SIMD instructions for 32-bit
data allowing operation on 128-bit vectors. For example the QMPY32 instruction is able to perform the
element to element multiplication between two vectors of four 32-bit data each.
C66x ISA includes a set of specific instructions to handle complex arithmetic and matrix operations.
330 Detailed Description
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