DRA790 Datasheet, PDF (381/436 Pages) Texas Instruments – Infotainment Applications Processor

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• Power Plane/Trace Effective Resistances
– From PMIC SMPS to SoC load = 9.7mohm
– From Power Inductor to SoC load = 6mohm
– "Open-Loop" Voltage/IR Drop for 1A = 6mV
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Figure 7-16. vdd Voltage/IR Drop [All Layers]
Dynamic analysis of this PCB design for the CORE power domain determined the vdd decoupling
capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop
inductance values ranged from 0.97 –1.75nH and were less than maximum 2.0nH recommended.
NOTE
Comparing loop inductances for capacitors at different distances from the SoC’s input power
balls shows an 18% reduction for caps placed closer. This was derived by averaging the
inductances for the 3 caps with distances over 800mils (Avg LL = 1.33nH) vs the 3 caps with
distances less than 600mils (Avg LL = 1.096nH).
Cap Ref Model Port Loop Inductacne
Des
#
[nH]
C487
10
0.97
C393
6
1.11
C394
7
1.12
C456
9
1.13
C386
3
1.16
C395
8
1.18
C363
1
1.46
C390
5
1.48
C364
2
1.74
Table 7-8. Rail - vdd
Footprint
Types
4vWSE
4vWSE
4vWSE
4vWSE
2vWSE
4vWSE
2vWSE
2vWSE
2vWSE
PCB Side
Top
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Distance to
Ball-Field
[mils]
521
358
357
403
40
460
40
40
40
Value [μF]
4.7
1.0
0.47
2.2
0.1
0.22
0.1
0.1
0.1
Size
0805
0603
0603
0603
0402
0603
0402
0402
0402
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Applications, Implementation, and Layout 381
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