DRA790 Datasheet, PDF (158/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
Figure 5-6. vddshv* Supplies Falling After vdds18v Supplies Delta
(1) Vdelta MAX = 2V
(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.
5.9.4 Clock Specifications
NOTE
For more information, see Power Reset and Clock Management / PRCM Environment /
External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock
Manager Functional Description section of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
• The system clocks, SYS_CLKIN1(Mandatory) and SYS_CLKIN2(Optional) are the main clock sources
of the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the
wake-up (WKUP) domain is supplied.
Figure 5-7 shows the external input clock sources and the output clocks to peripherals.
158 Specifications
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