DRA790 Datasheet, PDF (226/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
spim_cs(OUT)
PHA=0
EPOL=1
spim_sclk(OUT) ^POL=0
SM8
SM1
SM2
SM3
POL=1
spim_sclk(OUT)
spim_d(IN)
SM3
SM1
SM2
SM4
Bit n-1
SM5
SM4
Bit n-2
SM5
Bit n-3
Bit n-4
Bit 0
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SM9
spim_cs(OUT)
PHA=1
EPOL=1
spim_sclk(OUT) ^POL=0
SM8
POL=1
spim_sclk(OUT)
SM2
SM1
SM3
SM1
SM3
SM2
SM9
spim_d(IN)
SM5
SM4
Bit n-1
SM4
SM5
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-46. McSPI - Master Mode Receive
SPRS906_TIMING_McSPI_02
Table 5-62, Figure 5-47 and Figure 5-48 present Timing Requirements for McSPI - Slave Mode.
NO. PARAMETER
SS1 ⁽¹⁾ t_c(SPICLK)
SS2 ⁽¹⁾ t_w(SPICLKL)
SS3 ⁽¹⁾ t_w(SPICLKH)
SS4 ⁽¹⁾
SS5 ⁽¹⁾
SS6 ⁽¹⁾
t_{su(SIMO-SPICLK)}
t_{h(SPICLK-SIMO)}
t_{d(SPICLK-SOMI)}
Table 5-62. Timing Requirements for SPI - Slave Mode
DESCRIPTION
Cycle time, spi_sclk
Typical Pulse duration, spi_sclk low
Typical Pulse duration, spi_sclk high
Setup time, spi_d[x] valid before spi_sclk active edge
Hold time, spi_d[x] valid after spi_sclk active edge
Delay time, spi_sclk active edge to mcspi_somi transition
MODE
MIN
62.5 ⁽²⁾
(3)
0.45 × P
(4)
0.45 × P
(4)
5
5
SPI1/2/3
2
SPI4
2
MAX
26.6
20.1
UNIT
ns
ns
ns
ns
ns
ns
ns
226 Specifications
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