DRA790 Datasheet, PDF (141/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Instance Name
TIMER7
TIMER8
TIMER9
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
TIMER7_ICLK
TIMER7_FCLK
TIMER8_ICLK
TIMER8_FCLK
TIMER9_ICLK
TIMER9_FCLK
Clock
Type
Int
Func
Int
Func
Int
Func
Max. Clock
Allowed (MHz)
266
100
266
100
266
100
PRCM Clock Name
IPU_L3_GICLK
TIMER7_GFCLK
IPU_L3_GICLK
TIMER8_GFCLK
L4PER_L3_GICLK
TIMER9_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
PLL / OSC /
Source Name
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
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Specifications 141