DRA790 Datasheet, PDF (138/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-5. Maximum Supported Frequency (continued)
Module
Instance Name Input Clock Name
PCIESS1
PCIESS2
PRCM_MPU
PCIE1_PHY_WKU
P_CLK
PCIe_SS1_FICLK
PCIEPHY_CLK
PCIEPHY_CLK_DI
V
PCIE1_REF_CLKI
N
PCIE1_PWR_CLK
PCIE2_PHY_WKU
P_CLK
PCIe_SS2_FICLK
PCIEPHY_CLK
PCIEPHY_CLK_DI
V
PCIE2_REF_CLKI
N
PCIE2_PWR_CLK
32K_CLK
SYS_CLK
PWMSS1
PWMSS2
PWMSS3
QSPI
PWMSS1_GICLK
PWMSS2_GICLK
PWMSS3_GICLK
QSPI_ICLK
QSPI_FCLK
RNG
SAR_ROM
SDMA
RNG_ICLK
PRCM_ROM_CLO
CK
SDMA_FCLK
SHA2MD51
SHA2MD52
SL2
SMARTREFLEX_C
ORE
SHAM_1_CLK
SHAM_2_CLK
IVA_GCLK
MCLK
SYSCLK
SMARTREFLEX_D
SP
MCLK
SYSCLK
Clock
Type
Func
Int
Func
Func
Func
Func
Func
Func
Func
Func
Func
Func
Func
Func
Int &
Func
Int &
Func
Int &
Func
Int
Func
Int
Int
Int &
Func
Int
Int
Int
Int
Func
Int
Func
Max. Clock
Allowed (MHz)
0.032
PRCM Clock Name
PCIE_32K_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
FUNC_32K_CLK
266
2500
1250
34.3
38.4
0.032
PCIE_L3_GICLK
CORE_X2_CLK
PCIE_PHY_GCLK PCIE_PHY_GCLK
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE_REF_GFCLK CORE_USB_OTG_
SS_LFPS_TX_CLK
PCIE_SYS_GFCLK
SYS_CLK1
PCIE_32K_GFCLK FUNC_32K_CLK
266
2500
1250
34.3
38.4
0.032
38.4
266
PCIE_L3_GICLK
CORE_X2_CLK
PCIE_PHY_GCLK PCIE_PHY_GCLK
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE_REF_GFCLK CORE_USB_OTG_
SS_LFPS_TX_CLK
PCIE_SYS_GFCLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK1/610
WKUPAON_ICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
L4PER2_L3_GICLK CORE_X2_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
128
QSPI_GFCLK
FUNC_256M_CLK
PER_QSPI_CLK
266
L4SEC_L3_GICLK
CORE_X2_CLK
266
L4CFG_L3_GICLK
CORE_X2_CLK
266
DMA_L3_GICLK
CORE_X2_CLK
266
266
IVA_GCLK
133
38.4
133
38.4
L4SEC_L3_GICLK
L4SEC_L3_GICLK
IVA_GCLK
COREAON_L4_GICLK
WKUPAON_ICLK
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
CORE_X2_CLK
IVA_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_CORE
APLL_PCIE
APLL_PCIE
DPLL_CORE
OSC1
DPLL_CORE
APLL_PCIE
APLL_PCIE
DPLL_CORE
OSC1
OSC1
OSC1
DPLL_ABE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_IVA
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
138 Specifications
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