DRA790 Datasheet, PDF (379/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
NOTE
For more information about Input Voltage Sources, see Section 5.9.4.3 DPLLs, DLLs
Specifications.
Table 7-6 presents the voltage inputs that supply the DPLLs.
Table 7-6. Input Voltage Power Supplies for the DPLLs
POWER SUPPLY
vdda_per
vdda_ddr
vdda_debug
vdda_core_gmac
vdda_gpu
vdda_video
vdda_mpu_abe
vdda_osc
vdda_dsp_iva
DPLLs
DPLL_PER and PER HSDIVIDER analog power supply
DPLL_DDR and DDR HSDIVIDER analog power supply
DPLL_DEBUG analog power supply
DPLL_CORE and HSDIVIDER analog power supply
DPLL_GPU analog power supply
DPLL_VIDEO1 analog power supply
DPLL_MPU and DPLL_ABE analog power supply
not DPLL input but is required to be supplied by low noise input voltage
DSP PLL and IVA PLL analog power supply
7.3.7 Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the vdd
processor power domain.
NOTE
Materials presented in this section are based on generic PDN analysis on PCB boards and
are not specific to systems integrating the Device.
7.3.7.1 Example Stack-up
Layer Assignments:
• Layer Top: Signal and Segmented Power Plane
– Processor and PMIC components placed on Top-side
• Layer 2: Gnd Plane1
• Layer 3: Signals
• Layer n: Power Plane1
• Layer n+1: Power Plane 2
• Layer n+2: Signal
• Layer n+3: Gnd Plane2
• Layer Bottom: Signal and Segmented Power Planes
– Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
• ½ oz for all signal layers.
• 1-2oz for all power plane for improved PCB heat spreading.
7.3.7.2 vdd Example Analysis
Maximum acceptable PCB resistance (R_eff) between the PMIC and Processor input power balls should not
exceed 10mΩ.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 379
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