DRA790 Datasheet, PDF (407/436 Pages) Texas Instruments – Infotainment Applications Processor

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32-bit DDR3 EMIF
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
ddr1_d31
8
ddr1_d24
ddr1_dqm3
ddr1_dqs3
ddr1_dqsn3
ddr1_d23
8
ddr1_d16
ddr1_dqm2
ddr1_dqs2
ddr1_dqsn2
ddr1_d15
8
ddr1_d8
ddr1_dqm1
ddr1_dqs1
ddr1_dqsn1
ddr1_d7
8
ddr1_d0
ddr1_dqm0
ddr1_dqs0
ddr1_dqsn0
ddr1_ck
ddr1_nck
ddr1_odt0
ddr1_csn0
ddr1_odt1
ddr1_csn1
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_a0
NC
NC
16
ddr1_a15
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_cke
ddr1_rst
ddr1_vref0
0.1 µF
DQ15
DQ8
UDM
UDQS
UDQS
DQ7
DQ0
LDM
LDQS
LDQS
CK
CK
ODT
CS
16-Bit DDR3
Devices
DQ15
DQ8
UDM
UDQS
UDQS
DQ7
D08
LDM
LDQS
LDQS
CK
CK
ODT
CS
BA0
BA1
BA2
A0
A15
CAS
RAS
WE
CKE
RST
ZQ
ZQ
VREFDQ
VREFCA
0.1 µF
BA0
BA1
BA2
A0
A15
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
0.1 µF
Zo ^{0.1 µF}
DDR_1V5
Zo
DDR_VTT
Zo
Zo
DDR_VREF
ZQ
Zo
Termination is required. See terminator comments.
ZQ
Value determined according to the DDR memory device data sheet.
SPRS906_PCB_DDR3_02
Figure 7-38. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
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Applications, Implementation, and Layout 407
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