DRA790 Datasheet, PDF (156/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Figure 5-4 and Figure 5-5, describe the device Power Sequencing.
vdds18v, vdds_mlbp, vdds18v_ddr1
Note 3
vdda_per, vdda_ddr, vdda_debug,
vdda_core_gmac, vdda_gpu,
vdda_video, vdda_osc, vdda_csi,
vdda_mpu_abe
vdds_ddr1, ddr1_vref0
vdd
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_usb3
vddshv1, vddshv3, vddshv4,
vddshv7, vddshv9,
vddshv10, vddshv11
VD_CORE BOOT voltage
VD_DSP BOOT voltage
Note 4
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vdda33v_usb1, vdda33v_usb2
vddshv8
Note 5
xi_osc0
Note 7
resetn/porz
Note 8
Note 9
sysboot[15:0]
Valid Config
Note 10
rstoutn
SPRS960_ELCH_04
Figure 5-4. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) vdd must ramp before or at the same time as vdd_dsp.
(4) If any of the vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can
be combined with vdds18v.
(5) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(6) vdds and vdda rails must not be combined together.
(7) Pulse duration: resetn/porz must remain low a minimum of 12P⁽¹¹⁾ after xi_osc0 is stable and at a valid frequency.
(8) Setup time: sysboot[15:0] pins must be valid 2P⁽¹¹⁾ before porz is de-asserted high.
(9) Hold time: sysboot[15:0] pins must be valid 15P⁽¹¹⁾ after porz is de-asserted high.
(10) resetn to rstoutn delay is 2ms.
156 Specifications
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