DRA790 Datasheet, PDF (338/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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• Two Interrupt outputs configured independently to service either ECC or CBUF interrupt events
The OCM controller does not have a memory protection logic and does not support endianism conversion.
For more information, see section On-Chip Memory (OCM) in chapter Memory Subsystem of the device
TRM.
6.8 Interprocessor Communication
6.8.1 MailBox
Communication between the on-chip processors of the device uses a queued mailbox-interrupt
mechanism.
The queued mailbox-interrupt mechanism allows the software to establish a communication channel
between two processors through a set of registers and associated interrupt signals by sending and
receiving messages (mailboxes).
The device implements the following mailbox types:
• System mailbox:
– Number of instances: 13
– Used for communication between: MPU, DSP1, IPU1, and IPU2 subsystems
– Reference name: MAILBOX(1..13)
Each mailbox module supports the following features:
• Parameters configurable at design time
– Number of users
– Number of mailbox message queues
– Number of messages (FIFO depth) for each message queue
• 32-bit message width
• Message reception and queue-not-full notification using interrupts
• Support of 16-/32-bit addressing scheme
• Power management support
For more information, see chapter MailBox of the device TRM.
6.8.2 Spinlock
The Spinlock module provides hardware assistance for synchronizing the processes running on multiple
processors in the device:
• Cortex®-A15 microprocessor unit (MPU) subsystem
• Digital signal processor (DSP) subsystem – DSP1
• Dual Cortex-M4 image processing unit (IPU) subsystems – IPU1 and IPU2
The Spinlock module implements 256 spinlocks (or hardware semaphores), which provide an efficient
way to perform a lock operation of a device resource using a single read-access, avoiding the need of
a readmodify- write bus transfer that the programmable cores are not capable of.
For more information, see chapter Spinlock Module of the device TRM.
6.9 Interrupt Controller
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
The MPU, DSP, and IPU (x2) subsystems are capable of servicing these interrupts via their integrated
interrupt controllers. In addition, each processor's interrupt controller is preceded by an Interrupt Controller
Crossbar (IRQ_CROSSBAR) that provides flexibility in mapping the device interrupts to processor
interrupt inputs. For more information about IRQ crossbar, see chapter Control Module of the Device
TRM.
338 Detailed Description
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