DRA790 Datasheet, PDF (380/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.0nH (ESL NOT included)
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 57mΩ at 20MHz.
Table 7-7. Example PCB vdd PI Analysis Summary
Parameter
OPP
Clocking Rate
Voltage Level
Max Current Draw
Max Effective Resistance: Power
Inductor Segment Total R_eff
Max Loop Inductance
Impedance Target
Recommendation
OPP_NOM
266 MHz
1V
1A
10mΩ
2.0nH
57mΩ F<20Mhz
Example PCB
1V
1A
9.7 mΩ
0.97 –1.75nH
57mΩ F<20Mhz
Figure 7-15 show a PCB layout example and the resulting PI analysis results.
PMIC
SMPS2
SMPS2_SW
L1002
1.0uH, 4.5A, 1616
IHLP-1616ABER1R0M11
CORE_VDD
C1014
47uF, 6.3V, X7R, 1210
GCM32ER70J476ME19
SoC
VDD
C363 , 364, 386, 388 ,
390, 498
0.1uF, 16V, X7R, 0402
GCM155R71C104KA55
C 395
0.22uF, 25V, X7R, 0603
GCM188R71E224KA55
C 394
0.47uF, 16V, X7R, 0603
GCM188R71C474KA55
C393
1.0uF, 16V, X7R, 0603
GCM188R71C105KA64
C456
2.2uF, 6.3V, X7R, 0603
GCM188R70J225KE22
Figure 7-15. vdd Simplified SCH Diagram
C487
4.7uF, 16V, X7R, 0805
GCM21BR71C475KA73
NOTE
PCB Etch Resistance Breakdown, PDN Effective Resistance, and vdd routings are UNDER
DEVELOPMENT!
IR Drop: vdd (PCB Rev Oct25, CAD sPSI v13.1.1)
• Source Conditions: 1V @ 1A
380 Applications, Implementation, and Layout
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