DRA790 Datasheet, PDF (411/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 7-29. Placement Specifications DDR3
NO.
PARAMETER
MIN MAX UNIT
KOD31 X1
500 Mils
KOD32 X2
600 Mils
KOD33 X3
600 Mils
KOD34 Y1
1800 Mils
KOD35 Y2
KOD36 DDR3 keepout region ⁽¹⁾
600 Mils
KOD37 Clearance from non-DDR3 signal
4
W
to DDR3 keepout region ^{(2) (3)}
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
7.7.2.8 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 7-41. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in Table 7-
29. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.
Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the
DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the
two signals from the DDR3 controller should be separated from each other by the specification in Table 7-
29 (see KOD37).
Figure 7-41. DDR3 Keepout Region
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