DRA790 Datasheet, PDF (186/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
D2
D1
D3
D4
vouti_clk
D6
vouti_clk
Falling-edge Clock Reference
Rising-edge Clock Reference
vouti_vsync
D6
vouti_hsync
vouti_d[23:0]
vouti_de
D5
data_1 data_2
D6
data_n
D6
vouti_fld
odd
even
SWPS049-018
Figure 5-18. DPI Video Output^(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
In Table 5-39 are presented the specific groupings of signals (IOSET) for use with VOUT2.
SIGNALS
vout2_d23
vout2_d22
vout2_d21
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_d13
vout2_d12
vout2_d11
vout2_d10
Table 5-39. VOUT2 IOSETs
BALL
C8
B9
A7
A9
A8
A11
F10
A10
B10
E10
D10
C10
B11
D11
IOSET1
MUX
4
4
4
4
4
4
4
4
4
4
4
4
4
4
186 Specifications
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