DRA790 Datasheet, PDF (413/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see Section 7.3, Core Power Domains.
7.7.2.10.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
7.7.2.11 Net Classes
Table 7-32 lists the clock net classes for the DDR3 interface. Table 7-33 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
Table 7-32. Clock Net Class Definitions
CLOCK NET CLASS processor PIN NAMES
CK
ddrx_ck/ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
DQS1
DQS2⁽¹⁾
DQS3⁽¹⁾
ddrx_dqs1 / ddrx_dqsn1
ddrx_dqs2 / ddrx_dqsn2
ddrx_dqs3 / ddrx_dqsn3
(1) Only used on 32-bit wide DDR3 memory systems.
Table 7-33. Signal Net Class Definitions
SIGNAL NET CLASS
ADDR_CTRL
ASSOCIATED CLOCK
NET CLASS
CK
DQ0
DQS0
DQ1
DQ2⁽¹⁾
DQ3⁽¹⁾
DQS1
DQS2
DQS3
(1) Only used on 32-bit wide DDR3 memory systems.
processor PIN NAMES
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
ddrx_d[7:0], ddrx_dqm0
ddrx_d[15:8], ddrx_dqm1
ddrx_d[23:16], ddrx_dqm2
ddrx_d[31:24], ddrx_dqm3
7.7.2.12 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
7.7.2.13 VREF_DDR Routing
ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the
processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the
DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF
bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing
congestion.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 413
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