DRA790 Datasheet, PDF (377/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
• Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
• Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
Table 7-3. Recommended PDN and Decoupling Characteristics ^(1)(2)(3)(4)
PDN Analysis:
Static
Dynamic
Number of Recommended Decoupling Capacitors
per Supply
Supply
Max R_eff
(5)
[mΩ]
Dec. Cap.
Max LL⁽⁶⁾
[nH]
Max
Impedance
[mΩ]
Frequency
range
of Interest
100
nF
220
nF
470
nF
1μF
2.2
μF
4.7
μF
[MHz]
10
μF
22
μF
vdd_dsp
22
2.5
54
≤20
6
1
1
1
1
1
1
vdd
18
2
57
≤20
6
1
1
1
1
1
vdds_ddr1
33
2.5
200
≤100
8
3
2
2
1
cap_vbbldo_dsp
N/A
6
N/A
N/A
1
cap_vbbldo_gpu
N/A
6
N/A
N/A
1
cap_vbbldo_iva
N/A
6
N/A
N/A
1
cap_vbbldo_mpu
N/A
6
N/A
N/A
1
cap_vddram_core1
N/A
6
N/A
N/A
1
cap_vddram_core3
N/A
6
N/A
N/A
1
cap_vddram_core4
N/A
6
N/A
N/A
1
cap_vddram_dsp
N/A
6
N/A
N/A
1
cap_vddram_gpu
N/A
6
N/A
N/A
1
cap_vddram_iva
N/A
6
N/A
N/A
1
cap_vddram_mpu
N/A
6
N/A
N/A
1
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Specifications chapter.
(4) Maximum static voltage drop allowed drives the maximum acceptable power net resistance (R_eff) between the PMIC or the external
SMPS and the processor power balls.
(5) Maximum R_eff (from SMPS to Processor) allows for max supply voltage drop when both remote voltage sensing very close to processor
power balls and TI recommended PMICs are used.
(6) Maximum Loop Inductance to each high-frequency (30-70MHz) decoupling capacitor.
7.3.5 Power Supply Mapping
TPS65919 or LP8733 are the Power Management ICs (PMICs) that should be used for the Device
designs. TI requires use of these PMICs for the following reasons:
• TI has validated their use with the Device
• Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
• Support for power sequencing requirements (refer to Section 5.9.3 Power Supply Sequences)
• Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
• Remote sensing at point of load with output voltage compensation allows for the maximum IR drop
budget
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Applications, Implementation, and Layout 377
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