DRA790 Datasheet, PDF (351/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
At system level the device supports PCI express interface in the following configurations:
• Each PCIe subsystem controller has support for PCIe Gen2 mode (5.0 Gbps per lane) and Gen1 mode
(2.5 Gbps per lane).
• One PCIe (PCIe_SS1) operates as Gen2 2-lanes supporting in either root-complex (RC) or end-point
EP.
• Two PCIe (PCIe_SS1 and PCIe_SS2) operates Gen2 1-lane supporting either RC or EP with the
possibility of one operating in Gen1 and one in Gen2.
• PCIe_SS1 can be configured to operate in either 2-Lane (dual lane) or 1-Lane (single lane) mode, as
follows:
– Single Lane - lane 0 mapped to the PCIe port 0 of the device
– Flexible dual lane configuration - lanes 0 and 1 can be swapped on the two PCIe ports
• PCIe_SS2 can only operate in 1-Lane mode, as follows:
– Single Lane - lane 0 mapped to the device PCIe port 1
When PCie_SS1 is configured to operate in dual-lane mode, PCIe_SS2 is in-operable as both
PCIe1_PHY_RX/TX and PCIe2_PHY_RX/TX are assigned to PCIe_SS1, and thereby NOT available to
PCIe_SS2.
The main features of a device PCIe controller are:
• 16-bit operation at 250 MHz on PIPE interface (per 16-bit lane)
• One master port on the L3_MAIN supporting 32-bit address and 64-bit data bus.
• PCIe_SS1 master port dedicated MMU (device MMU2) on L3_MAIN path, to which PCIe traffic can be
optionally mapped.
• One slave port on the L3_MAIN supporting 29-bit address and 64-bit data bus.
• Maximum outbound payload size of 64 Bytes (the L3 Interconnect PCIe1/2 target ports split bursts of
size >64 Bytes to the into multiple 64 Byte bursts)
• Maximum inbound payload size of 256 Bytes (internally converted to 128 Byte - bursts)
• No remote read request size limit: implicit support for 4 KiB-size and greater
• Support of EP legacy mode
• Support of inbound I/O accesses in EP legacy mode
• PIPE interface features fixed-width (16-bit data per lane) and dynamic frequency to switch between
PCIe Gen1 and Gen2.
• Ultra-low transmit and receive latency
• Automatic Lane reversal as specified in the PCI Express Base 3.0 Specification, revision 1.0 (transmit
and receive)
• Polarity inversion on receive
• Single Virtual Channel (VC0) and Single Traffic Class (TC0)
• Single Function in End point mode
• Automatic credit management
• ECRC generation and checking
• All PCI Device Power Management D-states with the exception of D3_cold/L2 state
• PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
• PCI Express Link Power Management states except for L2 state
• PCI Express Advanced Error Reporting (AER)
• PCI Express messages for both transmit and receive
• Filtering for Posted, Non-Posted, and Completion traffic
• Configurable BAR filtering, I/O filtering, configuration filtering and completion lookup/timeout
• Access to configuration space registers and external application memory mapped registers through
ECAM mechanism.
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Detailed Description 351