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5.9.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 5-43 and Table 5-44 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-19, Figure 5-20, Figure 5-21, Figure 5-22, Figure 5-23 and
Figure 5-24).
Table 5-43. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default
NO.
F12
F13
F21
F22
PARAMETER
t_su(dV-clkH)
t_h(clkH-dV)
t_{su(waitV-clkH)}
t_{h(clkH-waitV)}
DESCRIPTION
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
MIN
MAX UNIT
3
ns
1.1
ns
2.5
ns
1.3
ns
NOTE
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see the Device TRM.
Table 5-44. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default
NO. PARAMETER
DESCRIPTION
F0
t_c(clk)
Cycle time, output clock gpmc_clk period
F2
t_d(clkH-nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
F3
t_{d(clkH-nCSIV)}
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
F4
t_d(ADDV-clk)
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
F5
t_{d(clkH-ADDIV)}
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
F6
t_d(nBEV-clk)
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
F7
t_{d(clkH-nBEIV)}
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
F8
t_d(clkH-nADV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
F9 t_{d(clkH-nADVIV)} Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
F10
t_d(clkH-nOE)
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
F11
t_{d(clkH-nOEIV)}
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
F14
t_d(clkH-nWE)
Delay time, gpmc_clk rising edge to gpmc_wen transition
F15
t_d(clkH-Data)
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
F17
t_d(clkH-nBE)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
F18
t_w(nCSV)
Pulse duration, gpmc_cs[7:0] low
F19
t_w(nBEV)
Pulse duration, gpmc_ben[1:0] low
F20
t_w(nADVV)
Pulse duration, gpmc_advn_ale low
F23
t_d(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16 transition
MIN
11.3
F-1.7 ⁽⁷⁾
E-1.7 ⁽⁶⁾
B-1.8 ⁽³⁾
-1.8
B-4.3⁽³⁾
D-1.5⁽⁵⁾
G-1.3 ⁽⁸⁾
D-1.3 ⁽⁵⁾
H-1.0 ⁽⁹⁾
E-1.0 ⁽⁶⁾
I-0.9 ⁽¹⁰⁾
J-2.1 ⁽¹¹⁾
J-1.5 ⁽¹¹⁾
A ⁽²⁾
C ⁽⁴⁾
K ⁽¹²⁾
0.5
MAX
F+4.3 ⁽⁷⁾
E+4.2 ⁽⁶⁾
B+4.3 ⁽³⁾
B+1.5⁽³⁾
D+4.3⁽⁵⁾
G+4.2 ⁽⁸⁾
G+4.2 ⁽⁵⁾
H+3.2 ⁽⁹⁾
E+3.2 ⁽⁶⁾
I+4.2 ⁽¹⁰⁾
J+4.6 ⁽¹¹⁾
J+4.3 ⁽¹¹⁾
7.5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 5-45. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate
NO.
F12
F13
PARAMETER
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
MIN
MAX UNIT
2.5
ns
1.9
ns
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Specifications 193