DRA790 Datasheet, PDF (145/436 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Instance Name
WD_TIMER2
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
WD_TIMER2_ICLK
WD_TIMER2_FCL
K
Clock
Type
Int
Func
Clock Sources
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
38.4
WKUPAON_GICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
0.032
WKUPAON_SYS_GFC WKUPAON_32K_G
LK
FCLK
PLL / OSC /
Source Name
OSC1
DPLL_ABE
5.6 Power Consumption Summary
NOTE
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7 Electrical Characteristics
NOTE
The data specified in Section 5.7 through Section 5.7.3 are subject to change.
NOTE
The interfaces or signals described in Section 5.7 through Section 5.7.3 correspond to the
interfaces or signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
Table 5-6. LVCMOS DDR DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn0, ddr1_cke,
ddr1_odt0, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst;
Balls: AA23 / AC24 / AB24 / AD24 / AB23 / AC23 / AD23 / AE24 / AA24 / W25 / Y23 / AD25 / AC25 / AB25 / AA25 / W24 / W23 / U25 /
U24 / W21 / T22 / U22 / U23 / T21 / T23 / T25 / T24 / P21 / N21 / P22 / P23 / P24 / AC18 / AE19 / AD19 / AB19 / AD20 / AE20 / AA18 /
AA20 / Y21 / AC20 / AA21 / AC21 / AC22 / AC15 / AB15 / AC16 / AE23 / W22 / U21 / P25 / AE16 / AA16 / AB16 / AC19 / AB18 / AD18 /
AD16 / AD17 / AE18 / AE17;
Driver Mode
V_OH
V_OL
C_PAD
High-level output threshold (I_OH = 0.1 mA)
Low-level output threshold (I_OL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9 × VDDS
V
0.1 × VDDS
V
3
pF
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA790 DRA791 DRA793 DRA797
Specifications 145