DRA790 Datasheet, PDF (84/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
Table 4-14. McASP Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
mcasp5_axr0
McASP5 Transmit/Receive Data
IO
AA5
mcasp5_axr1
McASP5 Transmit/Receive Data
IO
AC4
mcasp5_axr2
McASP5 Transmit/Receive Data
IO
A17
mcasp5_axr3
McASP5 Transmit/Receive Data
IO
A16
mcasp5_fsx
McASP5 Transmit Frame Sync
IO
U6
mcasp5_ahclkx
mcasp5_aclkx⁽¹⁾
mcasp5_aclkr⁽¹⁾
McASP5 Transmit High-Frequency Master Clock
McASP5 Transmit Bit Clock
McASP5 Receive Bit Clock
O
J25
IO
AC3
IO
AC3
mcasp5_fsr
McASP5 Receive Frame Sync
IO
U6
Multichannel Audio Serial Port 6
mcasp6_axr0
McASP6 Transmit/Receive Data
IO
A18
mcasp6_axr1
McASP6 Transmit/Receive Data
IO
B17
mcasp6_axr2
McASP6 Transmit/Receive Data
IO
C14
mcasp6_axr3
McASP6 Transmit/Receive Data
IO
B15
mcasp6_ahclkx
mcasp6_aclkx⁽¹⁾
McASP6 Transmit High-Frequency Master Clock
McASP6 Transmit Bit Clock
O
J24
IO
B16
mcasp6_fsx
mcasp6_aclkr⁽¹⁾
McASP6 Transmit Frame Sync
McASP6 Receive Bit Clock
IO
B18
IO
B16
mcasp6_fsr
McASP6 Receive Frame Sync
IO
B18
Multichannel Audio Serial Port 7
mcasp7_aclkr⁽¹⁾ McASP7 Receive Bit Clock I/O
mcasp7_aclkx⁽¹⁾ McASP7 Transmit Bit Clock I/O
IO
E16
IO
E16
mcasp7_ahclkx McASP7 Transmit High-Frequency Master Clock
O
H24
mcasp7_axr0
McASP7 Transmit/Receive Data I/O
IO
A19
mcasp7_axr1
McASP7 Transmit/Receive Data I/O
IO
E17
mcasp7_axr2
McASP7 Transmit/Receive Data I/O
IO
D16
mcasp7_axr3
McASP7 Transmit/Receive Data I/O
IO
D17
mcasp7_fsr
McASP7 Receive Frame Sync I/O
IO
F16
mcasp7_fsx
McASP7 Transmit Frame Sync I/O
IO
F16
Multichannel Audio Serial Port 8
mcasp8_aclkr⁽¹⁾ McASP8 Receive Bit Clock I/O
mcasp8_aclkx⁽¹⁾ McASP8 Transmit Bit Clock I/O
IO
D20
IO
D20
mcasp8_ahclkx McASP8 Transmit High-Frequency Master Clock I/O
O
H25
mcasp8_axr0
McASP8 Transmit/Receive Data I/O
IO
B20
mcasp8_axr1
McASP8 Transmit/Receive Data I/O
IO
C19
mcasp8_fsr
McASP8 Receive Frame Sync I/O
IO
C20
mcasp8_fsx
McASP8 Transmit Frame Sync I/O
IO
C20
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
4.3.14 USB
NOTE
For more information, see: Serial Communication Interface / SuperSpeed USB DRD
Subsystem section of the device TRM.
84
Terminal Configuration and Functions
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