DRA790 Datasheet, PDF (339/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Cortex®-A15 MPU Subsystem Interrupt Controller (MPU_INTC)
The MPU_INTC module (also called Generalized Interrupt Controller [GIC]) is a single functional unit that
is integrated in the ARM ^® Cortex-A15 multiprocessor core (MPCore) alongside Cortex-A15 processor. It
provides:
• 160 hardware interrupt inputs
• Generation of interrupts by software
• Prioritization of interrupts
• Masking of any interrupts
• Distribution of the interrupts to the target Cortex-A15 processor(s)
• Tracking the status of interrupts
The Cortex-A15 processor supports three main groups of interrupt sources, with each interrupt source
having a unique ID:
• Software Generated Interrupts (SGIs): SGIs are generated by writing to the Cortex-A15 Software
Generated Interrupt Register (GICD_SGIR). A maximum of 16 SGIs (ID0–ID15) can be generated for
the CPU interface. An SGI has edge-triggered properties. The software triggering of the interrupt is
equivalent to the edge transition of the interrupt signal on a peripheral input.
• Private Peripheral Interrupts (PPIs): A PPI is an interrupt generated by a peripheral that is specific to
the processor. Although interrupts ID16–ID31 are dedicated to PPIs in general, only seven PPIs are
actually used for the CPU interface (ID25–ID31). Interrupts ID16–ID24 are reserved (not used).
• Shared Peripheral Interrupts (SPIs): SPIs are triggered by events generated on associated interrupt
input lines. In this device, the GIC is configured to support 160 SPIs corresponding to its external
IRQS[159:0] signals.
For detailed information about this module and description of SGIs and PPIs, see the ARM Cortex-A15
MPCore Technical Reference Manual (available at infocenter.arm.com/help/index.jsp).
C66x DSP Subsystem Interrupt Controller (DSP1_INTC)
The DSP1 subsystem integrates an interrupt controller - DSP1_INTC, which interfaces the system events
to the C66x core interrupt and exceptions inputs. It combines up to 128 interrupts into 12 prioritized
interrupts presented to the C66x CPU.
For detailed information about this module, see chapter DSP Subsystem of the Device TRM.
Dual Cortex-M4 IPU Subsystem Interrupt Controller (IPUx_Cx_INTC, where x = 1, 2)
There are two Image Processing Unit (IPU) subsystems in the device - IPU1, and IPU2. Each IPU
subsystem integrates two ARM Cortex-M4 cores.
A Nested Vectored Interrupt Controller (NVIC) is integrated within each Cortex-M4. The interrupt mapping
is the same (per IPU) for the two cores to facilitate parallel processing. The NVIC supports:
• 64 external interrupts (in addition to 16 Cortex-M4 internal interrupts), which are dynamically prioritized
with 16 levels of priority defined for each core
• Low-latency exception and interrupt handling
• Prioritization and handling of exceptions
• Control of the local power management
• Debug accesses to the processor core
For detailed information about this module, refer to ARM Cortex-M4 Technical Reference Manual
(available at infocenter.arm.com/help/index.jsp).
6.10 EDMA
The primary purpose of the Enhanced Direct Memory Access (EDMA) controller is to service user-
programmed data transfers between two memory-mapped slave endpoints on the device.
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