DRA790 Datasheet, PDF (350/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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6.11.10 PCIe
The Peripheral Component Interconnect Express (PCIe) module is a multi-lane I/O interconnect that
provides low pin-count, high reliability, and high-speed data transfer at rates of up to 5.0 Gbps per lane,
per direction, for serial links on backplanes and printed wiring boards. It is a 3-rd Generation I/O
Interconnect technology succeeding PCI and ISA bus that is designed to be used as a general-purpose
serial I/O interconnect. It is also used as a bridge to other interconnects like USB2/3.0, GbE MAC, and so
forth.
The PCI Express standard predecessor - PCI, is a parallel bus architecture that is increasingly difficult to
scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. The PCIe
architecture was developed to help minimize I/O bus bottlenecks within systems and to provide the
necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. It
is designed to replace the PCI-based shared, parallel bus signaling technology that is approaching its
practical performance limits while simplifying the interface design.
The device instantiates two PCIe subsystems (PCIe_SS1 and PCIe_SS2). The PCIe controller is capable
to operate either in Root Complex (RC) or in End Point (EP) PCIe mode. The device PCIe_SS1 controller
supports up to two 16-bit data lanes on its PIPE port. The device PCIe_SS2 controller supports only one
16-bit data lane on its PIPE port.
When the PCIe_SS1 controller PIPE port is configured to operate in a single-lane mode, it operates on a
single pair of PCIe PHY serializer and deserializer - PCIe1_PHY_TX/PCIe1_PHY_RX. When PCIe_SS1
PIPE is configured to operate in dual-lane mode, it operates on two pairs of PCIe PHY serializer and
deserializer - PCIe1_PHY_TX/PCIe1_PHY_RX and PCIe2_PHY_TX/PCIe2_PHY_RX, respectively. The
single-lane PCIe_SS2 controller PIPE port (if enabled) can operate only on the
PCIe2_PHY_TX/PCIe2_PHY_RX pair. Hereby, if PCIe_SS2 controller is used, the PCIe_SS1 can operate
only in a single-lane mode on the PCIe1_PHY_TX/PCIe1_PHY_RX. In addition, PCIe PHY subsystem
encompasses a PCIe PCS (physical coding sublayer), a PCIe power management logic, APLL, a DPLL
reference clock generator and an APLL clock low-jitter buffer.
• The PCIe Controller implements the transport and link layers of the PCIe interface protocol.
• PCIe PCS (a physical coding sublayer component) converts a 8-bit portion of parallel data over a PCIe
lane to a 10-bit parallel data to adapt the process of serialization and deserialization in the TX/RX
PHYs to various requirements. At the same time it transforms the transmission rate to maintain the
PCIe Gen2 bandwidth (5 Gbps) on both sides (PCIe controller and PHY).
• A multiplexer logic which adds flexibility to connect a PCIe controller hardware mapped PCS logic
output to a single (for the single-lane PCIe_SS2 controller) or to a couple (for the 2-lane PCIe_SS1
controller) of PHY ports at a time
• Physical layer (PHY) serializer/deserializer components with associated power control logic, building
the so called PMA (physical media attachment) part of the PCIe_PHY transceiver, as follows:
– PCIe physical port 0 associated serializer (TX) - PCIe1_PHY_TX and deserializer (RX) -
PCIe1_PHY_RX
– PCIe physical port 1 associated serializer (TX) - PCIe2_PHY_TX and deserializer (RX) -
PCIe2_PHY_RX
• DPLL_PCIe_REF is a DPLL clock source, controlled from the device PRCM, that provides a 100-MHz
clock to the PCIe PHY serializer/deserializer components reference clock inputs.
• Both the PCIe_SS1 and PCIe_SS2 share the same APLL (APLLPCIe) which by default multiplies the
DPLL_PCIe_REF (typically 100 MHz or 20 MHz) clock to 2.5 GHz.
• The APLLPCIe low-jitter buffer (ACSPCIE) and additional logic takes care to provide the PCIe APLL
reference input clock.
PCIe module supports the following features:
• PCI Local Bus Specification revision 3.0
• PCI Express Base 3.0 Specification, revision 1.0.
350 Detailed Description
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