DRA790 Datasheet, PDF (253/436 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
5.9.6.16 USB
SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions:
• USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY.
• USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.
• USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
PHYs.
NOTE
For more information, see the SuperSpeed USB DRD section of the Device TRM.
5.9.6.16.1 USB1 DRD PHY
The USB1 DRD interface supports the following applications:
• USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
• USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is
compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate
of 5Gbps.
5.9.6.16.2 USB2 PHY
The USB2 interface supports the following applications:
• USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
5.9.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
TheUSB3 DRD interfaces support the following application:
• USB ULPI port: this synchronous interface is compliant with the USB2.0 ULPI SDR standard (UTMI+
v1.22), for alternative off-chip USB2.0 PHY interface; that is, with external transceiver with a maximum
frequency of 60 MHz (synchronous slave mode, SDR, 12-pin, 8-data-bit).
NOTE
The Universal Serial Bus k ULPI modules are also refered as USBk where k = 3, 4.
Table 5-84, Table 5-85 and Figure 5-63 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 5-84. Timing Requirements for ULPI SDR Slave Mode
NO.
US1
US5
US6
US7
US8
PARAMETER
t_c(clk)
t_{su(ctrlV-clkH)}
t_{h(clkH-ctrlV)}
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
Cycle time, usb_ulpi_clk period
Setup time, usb_ulpi_dir/usb_ulpi_nxt valid before usb_ulpi_clk
rising edge
Hold time, usb_ulpi_dir/usb_ulpi_nxt valid after usb_ulpi_clk
rising edge
Setup time, usb_ulpi_d[7:0] valid before usb_ulpi_clk rising edge
Hold time, usb_ulpi_d[7:0] valid after usb_ulpi_clk rising edge
MIN
16.66
6.73
-0.41
6.73
-0.41
MAX
UNIT
ns
ns
ns
ns
ns
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA790 DRA791 DRA793 DRA797
Specifications 253