DRA790 Datasheet, PDF (278/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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SDR1041
SDR1042H
SDR1042L
mmc1_clk
SDR1045
SDR1045
mmc1_cmd
SDR1046
SDR1046
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_12
Figure 5-86. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode
5.9.6.21.1.7 UHS-I DDR50, 4-bit data
Table 5-127 and Table 5-128 present Timing requirements and Switching characteristics for MMC1 -
DDR50 in receiver and transmitter mode (see Figure 5-87 and Figure 5-88).
Table 5-127. Timing Requirements for MMC1 - SD Card DDR50 Mode
NO.
PARAME
TER
DESCRIPTION
DDR50 t_su(cmdV-clk) Setup time, mmc1_cmd valid before mmc1_clk
5
transition
DDR50 t_h(clk-cmdV) Hold time, mmc1_cmd valid after mmc1_clk transition
6
DDR50 t_su(dV-clk)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
transition
DDR50 t_h(clk-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk
transition
MODE
Pad Loopback
Internal Loopback
Pad Loopback
Internal Loopback
MIN
1.79
2
1.79
1.79
2
1.6
MAX UNIT
ns
ns
ns
ns
ns
ns
Table 5-128. Switching Characteristics for MMC1 - SD Card DDR50 Mode
NO. PARAMETER
DDR500 fop(clk)
DDR501 t_w(clkH)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
DDR502 t_w(clkL)
Pulse duration, mmc1_clk low
DDR503 t_d(clk-cmdV)
Delay time, mmc1_clk transition to mmc1_cmd transition
DDR504 t_d(clk-dV)
Delay time, mmc1_clk transition to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5 × P-
0.185 ⁽¹⁾
0.5 × P-
0.185 ⁽¹⁾
1.225
1.225
MAX
48
6.6
6.6
UNIT
MHz
ns
ns
ns
ns
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
DDR501
DDR507
DDR508
DDR500
DDR502
DDR505
DDR507
DDR508
DDR506
Figure 5-87. SDMMC - High Speed SD - DDR - Data/Command Receive
SPRS906_TIMING_MMC1_13
278 Specifications
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