DRA790 Datasheet, PDF (317/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET2
Direct Output mode. See Table 5-27 Modes Summary for a list of IO timings requiring the use of Manual
IO Timings Modes. See Table 5-193 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct
Output mode for a definition of the Manual modes.
Table 5-193 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 5-193. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode
BALL
BALL NAME
C16
mcasp1_aclkx
D14
mcasp1_axr0
B14
mcasp1_axr1
B16
mcasp1_axr10
B18
mcasp1_axr11
A19
mcasp1_axr12
E17
mcasp1_axr13
E16
mcasp1_axr14
A18
mcasp1_axr8
B17
mcasp1_axr9
D23
mcasp4_axr1
AC3
mcasp5_aclkx
AA5
mcasp5_axr0
AC4
mcasp5_axr1
U6
mcasp5_fsx
J25
xref_clk0
J24
xref_clk1
PR2_PRU1_DIR_OUT_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
200
800
200
1000
0
1110
0
2500
0
1900
0
2300
200
1200
200
1100
200
1600
0
1900
0
700
1400
4000
1500
3000
1500
1900
1300
2700
0
160
0
0
CFG REGISTER
CFG_MCASP1_ACLKX_OUT
CFG_MCASP1_AXR0_OUT
CFG_MCASP1_AXR1_OUT
CFG_MCASP1_AXR10_OUT
CFG_MCASP1_AXR11_OUT
CFG_MCASP1_AXR12_OUT
CFG_MCASP1_AXR13_OUT
CFG_MCASP1_AXR14_OUT
CFG_MCASP1_AXR8_OUT
CFG_MCASP1_AXR9_OUT
CFG_MCASP4_AXR1_OUT
CFG_MCASP5_ACLKX_OUT
CFG_MCASP5_AXR0_OUT
CFG_MCASP5_AXR1_OUT
CFG_MCASP5_FSX_OUT
CFG_XREF_CLK0_OUT
CFG_XREF_CLK1_OUT
MUXMODE
13
pr2_pru1_gpo7
pr2_pru1_gpo8
pr2_pru1_gpo9
pr2_pru1_gpo12
pr2_pru1_gpo13
pr2_pru1_gpo14
pr2_pru1_gpo15
pr2_pru1_gpo16
pr2_pru1_gpo10
pr2_pru1_gpo11
pr2_pru1_gpo0
pr2_pru1_gpo1
pr2_pru1_gpo3
pr2_pru1_gpo4
pr2_pru1_gpo2
pr2_pru1_gpo5
pr2_pru1_gpo6
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2
Parallel Capture Mode. See Table 5-27 Modes Summary for a list of IO timings requiring the use of
Manual IO Timings Modes. See Table 5-194 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2
Parallel Capture Mode for a definition of the Manual modes.
Table 5-194 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 5-194. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode
BALL
Y5
Y6
A21
A22
B22
B23
A23
Y2
Y1
Y4
AA2
BALL NAME
gpio6_10
gpio6_11
mcasp2_axr2
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mmc3_clk
mmc3_cmd
mmc3_dat0
mmc3_dat1
PR2_PRU0_PAR_CAP_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
4125
481
3935
997
0
0
571
0
1570
0
1405
0
1946
0
4093
1066
4043
921
4010
864
3817
1643
CFG REGISTER
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
CFG_MCASP2_AXR2_IN
CFG_MCASP3_ACLKX_IN
CFG_MCASP3_AXR0_IN
CFG_MCASP3_AXR1_IN
CFG_MCASP3_FSX_IN
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
MUXMODE
12
pr2_pru0_gpi0
pr2_pru0_gpi1
pr2_pru0_gpi16
pr2_pru0_gpi12
pr2_pru0_gpi14
pr2_pru0_gpi15
pr2_pru0_gpi13
pr2_pru0_gpi2
pr2_pru0_gpi3
pr2_pru0_gpi4
pr2_pru0_gpi5
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Specifications 317