DRA790 Datasheet, PDF (16/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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BALL NUMBER
[1]
BALL NAME [2]
T25
T24
P21
N21
P22
P23
P24
AE23
W22
U21
P25
AD22
Y24
V24
R24
AE22
Y25
V25
R25
AE21
AD18
AD17
AE17
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_nck
ddr1_odt0
ddr1_rasn
ddr1_rst
SIGNAL NAME [3]
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_nck
ddr1_odt0
ddr1_rasn
ddr1_rst
16
Terminal Configuration and Functions
Table 4-1. Pin Attributes⁽¹⁾ (continued)
Support [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
0
IO
PD
PD
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
O
PU
drive 1
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
O
PU
drive 1
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
O
PU
drive 1
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
O
PU
drive 1
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PU
PU
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PU
PU
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PU
PU
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PU
PU
1.2/1.5
vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
O
PU
drive 1
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
O
PD
drive 0
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
O
PU
drive 1
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
0
O
PD
drive 0
(OFF)
1.2/1.5
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
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