DRA790 Datasheet, PDF (140/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Instance Name
TIMER4
TIMER5
TIMER6
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
TIMER4_ICLK
TIMER4_FCLK
TIMER5_ICLK
TIMER5_FCLK
TIMER6_ICLK
TIMER6_FCLK
Clock
Type
Int
Func
Int
Func
Int
Func
Max. Clock
Allowed (MHz)
266
100
266
100
266
100
PRCM Clock Name
L4PER_L3_GICLK
TIMER4_GFCLK
IPU_L3_GICLK
TIMER5_GFCLK
IPU_L3_GICLK
TIMER6_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CLKOUTMUX[0]
PLL / OSC /
Source Name
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
140 Specifications
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