DRA790 Datasheet, PDF (221/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
HDQ
Command_byte_written
0_(LSB)
Break 1
6
t_RSPS
7_(MSB)
Data_byte_received
1
0_(LSB)
6
Figure 5-40. HDQ Communication Timing
SPRS906_TIMING_HDQ1W_04
5.9.6.11.2 HDQ/1-Wire—1-Wire Mode
Table 5-57 and Table 5-58 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-41, Figure 5-42 and Figure 5-43).
Table 5-57. HDQ / 1-Wire Timing Requirements - 1-Wire Mode
NO.
PARAMETER
DESCRIPTION
10
t_PDH
11
t_PDL
12
t_RDV
13
t_REL
Presence pulse delay high
Presence pulse delay low
Read data valid time
Read data release time
MIN
15
60
t_LOWR
0
MAX
60
240
15
45
UNIT
µs
µs
µs
µs
Table 5-58. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode
NO.
PARAMETER
DESCRIPTION
MIN
14 t_RSTL
Reset time low
480
15 t_RSTH
Reset time high
480
16 t_SLOT
Bit cycle time
60
17 t_LOW1
Write bit-one time
1
18 t_LOW0
Write bit-zero time⁽²⁾
60
19 t_REC
Recovery time
1
20 t_LOWR
Read bit strobe time⁽¹⁾
1
(1) t_LOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.
(2) t_LOWR must be less than t_SLOT.
MAX
960
120
15
120
15
UNIT
µs
µs
µs
µs
µs
µs
µs
1-WIRE
t_RTSL
t_PDH
t_RSTH
t_PDL
Figure 5-41. 1-Wire—Break (Reset)
SPRS906_TIMING_HDQ1W_05
1-WIRE
t
LOWR
t_RDV_and_t_REL
t_SLOT_and_t_REC
Figure 5-42. 1-Wire—Read Bit (Data)
SPRS906_TIMING_HDQ1W_06
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Specifications 221