DRA790 Datasheet, PDF (135/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Instance Name
McASP5
McASP6
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP5_AHCLKX
MCASP5_FCLK
MCASP5_ICLK
MCASP6_AHCLKX
MCASP6_FCLK
MCASP6_ICLK
Clock
Type
Func
Func
Int
Func
Func
Int
Clock Sources
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
100
MCASP5_AHCLKX DPLL_ABE_X2_CL
K
SYS_CLK1
FUNC_96M_AON_
CLK
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
MLBP_CLK
192
MCASP5_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
100
MCASP6_AHCLKX DPLL_ABE_X2_CL
K
FUNC_96M_AON_
CLK
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
MLB_CLK
MLBP_CLK
SYS_CLK1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
192
MCASP6_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
PLL / OSC /
Source Name
DPLL_ABE
OSC1
DPLL_PER
Module ATL
Module ATL
Module ATL
Module ATL
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
DPLL_PER
Module ATL
Module ATL
Module ATL
Module ATL
Module MLB
Module MLB
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE
DPLL_HDMI
DPLL_CORE
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Specifications 135