DRA790 Datasheet, PDF (171/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-27. Modes Summary (continued)
Virtual or Manual IO Mode Name
Data Manual Timing Mode
VIP_MANUAL14
VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings
VIP_MANUAL15
VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIP_MANUAL16
VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
PRU-ICSS
No Virtual or Manual IO Timing Mode Required All PRU_ICSS Modes not covered below
PR1_PRU1_DIR_IN_MANUAL
PRU-ICSS1 PRU1 Direct Input Mode Timings
PR1_PRU1_DIR_OUT_MANUAL
PRU-ICSS1 PRU1 Direct Output Mode Timings
PR1_PRU1_PAR_CAP_MANUAL
PRU-ICSS1 PRU1 Parallel Capture Mode Timings
PR2_PRU0_DIR_IN_MANUAL2
PRU-ICSS2 PRU0 IOSET2 Direct Input Mode Timings
PR2_PRU0_DIR_OUT_MANUAL2
PRU-ICSS2 PRU0 IOSET2 Direct Output Mode Timings
PR2_PRU1_DIR_IN_MANUAL1
PRU-ICSS2 PRU1 IOSET1 Direct Input Mode Timings
PR2_PRU1_DIR_IN_MANUAL2
PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings
PR2_PRU1_DIR_OUT_MANUAL1
PRU-ICSS2 PRU1 IOSET1 Direct Output Mode Timings
PR2_PRU1_DIR_OUT_MANUAL2
PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings
PR2_PRU0_PAR_CAP_MANUAL2
PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode Timings
PR2_PRU1_PAR_CAP_MANUAL1
PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode Timings
PR2_PRU1_PAR_CAP_MANUAL2
PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, PCIe, DCAN, GPIO, KBD, PWM, JTAG, TPIU, SDMA, INTC, MLB
No Virtual or Manual IO Timing Mode Required All Modes
5.9.6.3 VIP
The Device includes 1 Video Input Ports (VIP).
Table 5-28, Figure 5-16 and Figure 5-17 present timings and switching characteristics of the VIPs.
CAUTION
The I/O timings provided in this section are valid only for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in Table 5-29.
Table 5-28. Timing Requirements for VIP ^(3)(4)(5)
NO.
V1
V2
V3
PARAMETER
t_c(CLK)
t_w(CLKH)
t_w(CLKL)
DESCRIPTION
Cycle time, vinx_clki ^{(3) (5)}
Pulse duration, vinx_clki high ^{(3) (5)}
Pulse duration, vinx_clki low ^{(3) (5)}
V4
t_{su(CTL/DATA-CLK)}
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition ^{(3) (4) (5)}
V6
t_{h(CLK-CTL/DATA)}
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition ^{(3) (4) (5)}
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
MIN
6.06 ⁽²⁾
0.45 × P
(2)
0.45 × P
(2)
3.11 ⁽²⁾
-0.05 ⁽²⁾
MAX
UNIT
ns
ns
ns
ns
ns
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Specifications 171