DRA790 Datasheet, PDF (224/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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CAUTION
The I/O timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in
Table 5-63.
Table 5-61, Figure 5-45 and Figure 5-46 present Timing Requirements for McSPI - Master Mode.
Table 5-61. Timing Requirements for SPI - Master Mode ⁽¹⁾
NO.
SM1
PARAMETER
t_c(SPICLK)
SM2 t_w(SPICLKL)
SM3 t_w(SPICLKH)
SM4
SM5
SM6
t_{su(MISO-SPICLK)}
t_{h(SPICLK-MISO)}
t_{d(SPICLK-SIMO)}
DESCRIPTION
Cycle time, spi_sclk ^{(1) (2)}
Typical Pulse duration, spi_sclk low ⁽¹⁾
Typical Pulse duration, spi_sclk high ⁽¹⁾
Setup time, spi_d[x] valid before spi_sclk active edge ⁽¹⁾
Hold time, spi_d[x] valid after spi_sclk active edge ⁽¹⁾
Delay time, spi_sclk active edge to spi_d[x] transition ⁽¹⁾
SM7
SM8
t_d(CS-SIMO)
t_d(CS-SPICLK)
Delay time, spi_cs[x] active edge to spi_d[x] transition
Delay time, spi_cs[x] active to spi_sclk first edge ⁽¹⁾
SM9 t_d(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive ⁽¹⁾
MODE
SPI1/2/3/
4
MIN
20.8 ⁽³⁾
0.5 × P-1
(4)
0.5 × P-1
(4)
SPI1
SPI2
SPI3
SPI4
3.5
3.7
-3.57
-3.9
-4.9
-4.3
MASTER B-4.2 ⁽⁶⁾
_PHA0
(5)
MASTER A-4.2 ⁽⁷⁾
_PHA1
(5)
MASTER A-4.2 ⁽⁷⁾
_PHA0
(5)
MASTER B-4.2 ⁽⁶⁾
_PHA1
(5)
MAX
4.1
3.6
4.7
4.5
5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) 20.8ns cycle time = 48MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
224 Specifications
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