DRA790 Datasheet, PDF (304/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-176. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
NO. PARAMETER
1
t_{c(TX_CLK)}
2
t_{w(TX_CLKH)}
3
t_{w(TX_CLKL)}
4
t_{t(TX_CLK)}
DESCRIPTION
Cycle time, TX_CLK
Pulse duration, TX_CLK high
Pulse duration, TX_CLK low
Transition time, TX_CLK
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
399.96
39.996
140
14
140
14
MAX
400.04
40.004
260
26
260
26
3
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
1
2
4
3
MII_TXCLK
4
Figure 5-123. PRU-ICSS MII[x]_TXCLK Timing
SPRS91x_TIMING_PRU_MII_RT_05
Table 5-177. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
NO.
1
2
PARAMETER
t_{su(RXD-RX_CLK)}
t_{su(RX_DV-RX_CLK)}
t_{su(RX_ER-RX_CLK)}
t_{su(RXD-RX_CLK)}
t_{su(RX_DV-RX_CLK)}
t_{su(RX_ER-RX_CLK)}
t_{h(RX_CLK-RXD)}
t_{h(RX_CLK-RX_DV)}
t_{h(RX_CLK-RX_ER)}
t_{h(RX_CLK-RXD)}
t_{h(RX_CLK-RX_DV)}
t_{h(RX_CLK-RX_ER)}
DESCRIPTION
Setup time, RXD[3:0] valid before RX_CLK
Setup time, RX_DV valid before RX_CLK
Setup time, RX_ER valid before RX_CLK
Setup time, RXD[3:0] valid before RX_CLK
Setup time, RX_DV valid before RX_CLK
Setup time, RX_ER valid before RX_CLK
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
SPEED
10 Mbps
MIN MAX UNIT
8
ns
100 Mbps
8
ns
10 Mbps
8
ns
100 Mbps
8
ns
1
2
MII_MRCLK (Input)
MII_RXD[3:0],
MII_RXDV,
MII_RXER (Inputs)
SPRS91x_TIMING_PRU_MII_RT_06
Figure 5-124. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing
304 Specifications
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