DRA790 Datasheet, PDF (345/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
• Programmable divider clock source (2ⁿ where n = [0:7])
• On-the-fly read/write register (while counting)
• Subset programming model of the GP timer
• The watchdog timer is reset either on power on or after a warm reset before it starts counting.
• Reset or interrupt actions when a timer overflow condition occurs
• The watchdog timer generates a reset or an interrupt in its hardware integration.
For more information, see section Timers of the device TRM.
6.11.4 I2C
The device contains five multimaster high-speed (HS) inter-integrated circuit (I²C) controllers (I2Ci
modules, where i = 1, 2 ,3, 4, 5, 6) each of which provides an interface between a local host (LH), such as
a digital signal processor (DSP), and any I²C-bus-compatible device that connects through the I²C serial
bus. External components attached to the I²C bus can serially transmit and receive up to 8 bits of data to
and from the LH device through the 2-wire I²C interface.
Each multimaster HS I²C controller can be configured to act like a slave or master I²C-compatible device.
I²C1 and I²C2 controllers have dedicated I²C compliant open drain buffers, and support Fast mode (up to
400Kbps). I²C3, I²C4, I²C5 and I²C6 controllers are multiplexed with standard LVCMOS IO and connected
to emulate open drain. I²C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z
instead of driving high when transmitting logic 1. These controllers support HS mode (up to 3.4Mbps).
For more information, see section Multimaster High-Speed I2C Controller (I2C) in chapter Serial
Communication Interfaces of the device TRM.
6.11.5 UART
The UART is a simple L4 slave peripheral that utilizes the DMA_SYSTEM or EDMA for data transfer or
IRQ polling via CPU. There are 10 UART modules in the device. Only one UART supports IrDA features.
Each UART can be used for configuration and data exchange with a number of external peripheral
devices or interprocessor communication between devices.
6.11.5.1 UART Features
The UARTi (where i = 1 to 10) include the following features:
• 16C750 compatibility
• 64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
• Programmable interrupt trigger levels for FIFOs
• Baud generation based on programmable divisors N (where N = 1…16,384) operating from a fixed
functional clock of 48 MHz or 192 MHz
Oversampling is programmed by software as 16 or 13. Thus, the baud rate computation is one of two
options:
• Baud rate = (functional clock / 16) / N
• Baud rate = (functional clock / 13) / N
• This software programming mode enables higher baud rates with the same error amount without
changing the clock source
• Break character detection and generation
• Configurable data format:
– Data bit: 5, 6, 7, or 8 bits
– Parity bit: Even, odd, none
– Stop-bit: 1, 1.5, 2 bit(s)
• Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
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