DRA790 Datasheet, PDF (149/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-9. IHHV1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
Signal Names in MUXMODE 0: porz / wakeup3 / wakeup0;
Balls: AB10/AC10/F19;
1.8-V Mode
V_IH
V_IL
V_HYS
I_IN
C_PAD
3.3-V Mode
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
Pad capacitance (including package capacitance)
1.2
40
0.02
V_IH
Input high-level threshold
1.2
V_IL
Input low-level threshold
V_HYS
Input hysteresis voltage
40
I_IN
Input current at each I/O pin
5
C_PAD
Pad capacitance (including package capacitance)
MAX UNIT
V
0.4
V
mV
1
µA
1
pF
V
0.4
V
mV
8
µA
1
pF
Table 5-10. LVCMOS CSI2 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signals MUXMODE0 : csi2_0_dx[2:0]; csi2_0_dy[2:0];
Bottom Balls: AC1 / AB2 / AD1 / AC2 / AE2 / AD2
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
V_IH
Input high-level voltage
V_IL
Input low-level voltage
V_ITH
Input high-level threshold
V_ITL
Input low-level threshold
V_HYS
Input hysteresis
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)
880
1350
mV
550
mV
880
mV
550
mV
25
mV
V_IH
Input high-level voltage
V_IL
Input low-level voltage
V_ITH
Input high-level threshold
V_ITL
Input low-level threshold
V_HYS
Input hysteresis
MIPI D-PHY Mode High-Speed Receiver (HS-RX)
880
mV
300
mV
880
mV
300
mV
25
mV
V_IDTH
Differential input high-level threshold
70
mV
V_IDTL
Differential input low-level threshold
–70
mV
V_IDMAX Maximum differential input voltage
270
mV
V_IHHS
Single-ended input high voltage
460
mV
V_ILHS
Single-ended input low voltage
–40
mV
V_CMRXDC Differential input common-mode voltage
70
330
mV
Z_ID
Differential input impedance
80
100
125
Ω
(1) V_ITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. V_ITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, V_HYST. V_HYST is the difference
between the V_ITH threshold and the V_ITL threshold.
(4) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mV_PP beyond 450 MHz.
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Specifications 149