DRA790 Datasheet, PDF (316/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
Table 5-191. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode
BALL
C16
D14
B14
B16
B18
A19
E17
E16
A18
B17
D23
AC3
AA5
AC4
U6
J25
J24
BALL NAME
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr8
mcasp1_axr9
mcasp4_axr1
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
xref_clk0
xref_clk1
PR2_PRU1_DIR_IN_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
400
0
700
200
600
300
600
500
700
500
500
0
600
200
600
0
800
0
600
300
500
0
2100
1959
2300
2000
2300
1800
2100
1780
0
0
0
0
CFG REGISTER
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
CFG_MCASP1_AXR11_IN
CFG_MCASP1_AXR12_IN
CFG_MCASP1_AXR13_IN
CFG_MCASP1_AXR14_IN
CFG_MCASP1_AXR8_IN
CFG_MCASP1_AXR9_IN
CFG_MCASP4_AXR1_IN
CFG_MCASP5_ACLKX_IN
CFG_MCASP5_AXR0_IN
CFG_MCASP5_AXR1_IN
CFG_MCASP5_FSX_IN
CFG_XREF_CLK0_IN
CFG_XREF_CLK1_IN
MUXMODE
12
pr2_pru1_gpi7
pr2_pru1_gpi8
pr2_pru1_gpi9
pr2_pru1_gpi12
pr2_pru1_gpi13
pr2_pru1_gpi14
pr2_pru1_gpi15
pr2_pru1_gpi16
pr2_pru1_gpi10
pr2_pru1_gpi11
pr2_pru1_gpi0
pr2_pru1_gpi1
pr2_pru1_gpi3
pr2_pru1_gpi4
pr2_pru1_gpi2
pr2_pru1_gpi5
pr2_pru1_gpi6
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET1
Direct Output mode. See Table 5-27 Modes Summary for a list of IO timings requiring the use of Manual
IO Timings Modes. See Table 5-192 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct
Output mode for a definition of the Manual modes.
Table 5-192 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 5-192. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode
BALL
P5
L6
L5
N2
P2
N4
N3
P1
N1
T4
T5
R1
R2
P3
P4
N5
N6
BALL NAME
RMII_MHZ_50_CLK
mdio_d
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
uart3_txd
PR2_PRU1_DIR_OUT_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
2306
100
1900
2000
2000
1100
2000
1200
2000
1700
2000
1000
2200
1000
2200
1300
2250
1100
2350
1000
2000
1200
2000
1500
1850
1000
2100
1100
2200
1000
2000
1600
2000
1000
CFG REGISTER
CFG_RMII_MHZ_50_CLK_OUT
CFG_MDIO_D_OUT
CFG_MDIO_MCLK_OUT
CFG_RGMII0_RXC_OUT
CFG_RGMII0_RXCTL_OUT
CFG_RGMII0_RXD0_OUT
CFG_RGMII0_RXD1_OUT
CFG_RGMII0_RXD2_OUT
CFG_RGMII0_RXD3_OUT
CFG_RGMII0_TXC_OUT
CFG_RGMII0_TXCTL_OUT
CFG_RGMII0_TXD0_OUT
CFG_RGMII0_TXD1_OUT
CFG_RGMII0_TXD2_OUT
CFG_RGMII0_TXD3_OUT
CFG_UART3_RXD_OUT
CFG_UART3_TXD_OUT
MUXMODE
13
pr2_pru1_gpo2
pr2_pru1_gpo1
pr2_pru1_gpo0
pr2_pru1_gpo11
pr2_pru1_gpo12
pr2_pru1_gpo16
pr2_pru1_gpo15
pr2_pru1_gpo14
pr2_pru1_gpo13
pr2_pru1_gpo5
pr2_pru1_gpo6
pr2_pru1_gpo10
pr2_pru1_gpo9
pr2_pru1_gpo8
pr2_pru1_gpo7
pr2_pru1_gpo3
pr2_pru1_gpo4
316 Specifications
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