DRA790 Datasheet, PDF (276/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-123. Switching Characteristics for MMC1 - SD Card SDR25 Mode (continued)
NO. PARAMETER
DESCRIPTION
MIN
SDR256 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
(1) P = output mmc1_clk period in ns
MAX
6.6
UNIT
ns
SDR251
SDR252L
SDR252H
mmc1_clk
SDR253
SDR254
mmc1_cmd
SDR257
SDR258
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_07
Figure 5-81. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR251
SDR252H
SDR252L
HSSDR255
SDR255
SDR256
SDR256
SPRS906_TIMING_MMC1_08
Figure 5-82. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
5.9.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
Table 5-124 and Table 5-125 present Timing requirements and Switching characteristics for MMC1 -
SDR50 in receiver and transmitter mode (see Figure 5-83 and Figure 5-84).
Table 5-124. Timing Requirements for MMC1 - SD Card SDR50 Mode
NO. PARAMETER
SDR50 t_{su(cmdV-clkH)}
3
SDR50 t_h(clkH-cmdV)
4
SDR50 t_su(dV-clkH)
7
SDR50 t_h(clkH-dV)
8
DESCRIPTION
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
MODE
Pad Loopback Clock
Internal Loopback Clock
MIN
1.48
1.7
1.48
1.7
1.6
MAX UNIT
ns
ns
ns
ns
ns
Table 5-125. Switching Characteristics for MMC1 - SD Card SDR50 Mode
NO. PARAMETER
SDR501 fop(clk)
SDR502 t_w(clkH)
H
SDR502L t_w(clkL)
SDR505 t_d(clkL-cmdV)
SDR506 t_d(clkL-dV)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
Pulse duration, mmc1_clk low
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
MIN
0.5 × P-
0.185 ⁽¹⁾
0.5 × P-
0.185 ⁽¹⁾
-8.8
-3.66
MAX
96
6.6
1.46
UNIT
MHz
ns
ns
ns
ns
276 Specifications
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