DRA790 Datasheet, PDF (340/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Typical usage of the EDMA controller includes:
• Servicing software-driven paging transfers (for example, data movement between external memory
[such as SDRAM] and internal memory [such as DSP L2 SRAM])
• Servicing event-driven peripherals, such as a serial port
• Performing sorting or sub-frame extraction of various data structures
• Offloading data transfers from the main device CPUs, such as the C66x DSP CorePac or the ARM
CorePac
The EDMA controller consists of two major principle blocks:
• EDMA Channel Controller
• EDMA Transfer Controller(s)
The EDMA Channel Controller (EDMACC) serves as the user interface for the EDMA controller. The
EDMACC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers.
The EDMACC serves to prioritize incoming software requests or events from peripherals and submits
transfer requests (TR) to the EDMA transfer controller.
The EDMA Transfer Controller (EDMATC) is responsible for data movement. The transfer request packets
(TRP) submitted by the EDMACC contain the transfer context, based on which the transfer controller
issues read/write commands to the source and destination addresses programmed for a given transfer.
There are two EDMA controllers present on this device:
• EDMA_0, integrating:
– 1 Channel Controller, referenced as: EDMACC_0
– 2 Transfer Controllers, referenced as: EDMACC_0_TC_0 (or EDMATC_0) and EDMACC_0_TC_1
(or EDMATC_1)
• EDMA_1, integrating:
– 1 Channel Controller, referenced as: EDMACC_1
– 2 Transfer Controllers, referenced as: EDMACC_1_TC_0 (or EDMATC_2) and EDMACC_1_TC_1
(or EDMATC_3)
The two EDMA channel controllers (EDMACC_0 and EDMACC_1) are functionally identical. For
simplification, the unified name EDMACC shall be regularly used throughout this chapter when referring to
EDMA Channel Controllers functionality and features.
The four EDMA transfer controllers (EDMACC_0_TC_0, EDMACC_0_TC_1, EDMACC_1_TC_0 and
EDMACC_1_TC_1) are functionally identical. For simplification, the unified name EDMATC shall be
regularly used throughout this chapter when referring to EDMA Transfer Controllers functionality and
features.
Each EDMACC has the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
• Array (multiple bytes)
• Frame (multiple arrays)
• Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition
– Increment or constant addressing modes
– Linking mechanism allows automatic PaRAM set update
– Chaining allows multiple transfers to execute with one event
340 Detailed Description
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