XRT72L56 Datasheet, PDF (98/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
Bit 0 - P-Bit Error Interrupt Status
This Reset Upon Read bit-field indicates whether or
not the Detection of P-bit error interrupt has occurred
since the last read of this register. This bit-field will
be "0" if the Detection of P-bit error interrupt has NOT
occurred since the last read of this register. This bit-
field will be set to "1", if this interrupt has occurred
since the last read of this register. The Detection of
P-bit Error interrupt will occur if the Receive DS3/E3
Framer Block detects a P-bit error in the incoming
DS3 frame.
NOTE: For more information into the role of P-bits please
see Section 3.3.2.6.1.
3.3.2.11 Receive DS3 Sync Detect Enable Register
RxDS3 Sync Detect Enable Register (Address =
0x14)
RXDS3 SYNC DETECT ENABLE REGISTER (ADDRESS = 0X14)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
Enable F[4]
R/W
1
BIT 3
Enable F[3]
R/W
1
BIT 2
Enable F[2]
R/W
1
BIT 1
Enable F[1]
R/W
1
BIT 0
Enable F[0]
R/W
1
Bits 4 - 0 Enable5 F(4)- F(0)
These Read/Write bit-fields allows the user to enable
or disable the 5 parallel searches for valid M and F-
bit, while the Receive DS3 Framer is operating in the
RXDS3 FEAC REGISTER (ADDRESS = 0X16)
Frame Acquisition mode. For proper operation, the
user is highly encouraged to ensure that all of these
bit-fields are set to "1".
2.4.2.12 Receive DS3 FEAC Register
BIT 7
Not Used
RO
0
BIT 6
RO
1
BIT 5
RO
1
BIT 4
BIT 3
RxFEAC[5:0]
RO
R/O
1
1
BIT 2
R/O
1
BIT 1
R/O
1
BIT 0
Not Used
R/O
0
This Read/Write register contains the latest 6-bit
FEAC code that has been received and validated by
the Receive FEAC Processor. The contents of this
register will be cleared if the previously validated
code has been removed by the FEAC Processor.
NOTES:
1. For more information on the operation of the
Receive FEAC Processor, please see Section
3.3.3.1.
2. This register is only valid if the Channel has been
configured to operate in the DS3, C-bit Parity Fram-
ing format.
2.4.2.13 Receive DS3 FEAC Interrupt Enable/
Status Register
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FEAC Valid
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
Status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
RO
RO
RO
RO
R/W
RUR
R/W
RUR
0
0
0
0
0
0
0
0
Bit 4 - FEAC Valid
This Read Only bit is set to "1" when an incoming
FEAC Message Code has been validated by the Re-
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