XRT72L56 Datasheet, PDF (6/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
TXE3 TTB-5 REGISTER (ADDRESS = 0X3D) .......................................................................................... 113
TXE3 TTB-6 REGISTER (ADDRESS = 0X3E) ........................................................................................... 113
TXE3 TTB-7 REGISTER (ADDRESS = 0X3F) ........................................................................................... 113
TXE3 TTB-8 REGISTER (ADDRESS = 0X40) ........................................................................................... 114
TXE3 TTB-9 REGISTER (ADDRESS = 0X41) ........................................................................................... 114
TXE3 TTB-10 REGISTER (ADDRESS = 0X42) ......................................................................................... 115
TXE3 TTB-11 REGISTER (ADDRESS = 0X43) ......................................................................................... 115
TXE3 TTB-12 REGISTER (ADDRESS = 0X44) ......................................................................................... 115
TXE3 TTB-13 REGISTER (ADDRESS = 0X45) ......................................................................................... 116
TXE3 TTB-14 REGISTER (ADDRESS = 0X46) ......................................................................................... 116
TXE3 TTB-15 REGISTER (ADDRESS = 0X47) ......................................................................................... 116
TXE3 FA1 ERROR MASK REGISTER (ADDRESS = 0X48) ......................................................................... 117
TXE3 FA2 ERROR MASK REGISTER (ADDRESS = 0X49) ......................................................................... 117
TXE3 BIP-8 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 117
2.4.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ................................................................. 118
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 118
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) .................................................................. 119
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 120
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) ................................................................................ 121
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ................................................................... 121
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ................................................................... 121
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 122
2.4.8 Performance Monitor Registers ............................................................................................................. 122
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51) ........................................................... 122
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ................................... 123
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) .................................... 123
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ..................................................... 123
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ...................................................... 123
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56) ........................................................ 124
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57) ......................................................... 124
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58) ..................................................... 124
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59) ...................................................... 125
PMON HOLDING REGISTER (ADDRESS = 0X6C) ..................................................................................... 125
ONE-SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D) ................................................................ 125
LCV - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X6E) ............................................ 126
LCV - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X6F) .............................................. 126
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X70) ................ 126
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X71) ................. 127
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X72) ............... 127
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73) ................. 127
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) ............................................................................ 128
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ............................................................................. 130
HDLC CONTROL REGISTER (ADDRESS = 0X82) ..................................................................................... 131
2.5 THE LOSS OF CLOCK ENABLE FEATURE ............................................................................................................. 131
ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER .............................................................................. 132
2.6 USING THE PMON HOLDING REGISTER .............................................................................................................. 132
2.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER MICROPROCESSOR INTERFACE SECTION ................................. 132
TABLE 6: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN EACH CHANNEL
OF THE XRT72L56 FRAMER DEVICE ...................................................................................................... 133
TABLE 7: A LISTING OF THE XRT72L56 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICA-
TIONS) ................................................................................................................................................... 133
TABLE 8: A LISTING OF THE XRT72L56 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR E3, ITU-T G.832
APPLICATIONS) ...................................................................................................................................... 133
TABLE 9: A LISTING OF THE XRT72L56 FRAMER DEVICE INTERRUPT BLOCK REGISTER (FOR E3, ITU-T G.751
APPLICATIONS) ...................................................................................................................................... 134
IV