XRT72L56 Datasheet, PDF (114/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
October 1998 Revision of the ITU-T G.832 Framing format
for E3.
Bits 3-0 - RxSSM[3:0] - Received Synchronization
Status Message
These four Read-Only bits reflect the content of the
SSM, which is currently being received via the in-
bound E3 data stream.
NOTE: These four bit-fields are only valid if the Receive
Section of the Channel has been configured to support the
October 1998 Revision of the ITU-T G.832 Framing format
for E3.
2.4.4 Receive E3 Framer Configuration Regis-
ters (ITU-T G.751)
2.4.4.1 Receive E3 Framer Configuration &
Status Register - 1 (E3, ITU-T G.751)
RXE3 CONFIGURATION & STATUS REGISTER - 1 G.751 (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Reserved
RxFERF
Algo
Reserved
RO
RO
RO
R/W
RO
RO
0
0
0
0
0
0
BIT 1
RO
0
BIT 0
RxBIP4
R/W
0
Bit 4 - RxFERF Algo(rithm) Select
This Read/Write bit-field permits the user to select
the Received FERF Declaration Algorithm.
Setting this bit-field to "0", configures the Receive
Section of the Channel to declare a FERF (Far-End-
Receive Failure), after three (3) consecutive E3
frames, with the A-bit set to "1", have been received.
Further, the Receive Section of the Channel will clear
FERF, after three (3) consecutive E3 frames, with the
A-bit set to "0", have been received.
Setting this bit-field to "1", configures the Receive
Section of the Channel to declare a FERF, after five
(5) consecutive E3 frames, with the A-bit set to "1",
have been received. Further, the Receive Section of
the Channel will clear FERF after five (5) consecutive
E3 frames, with the A-bit set to "0", have been re-
ceived.
Bit 0 - RxBIP4 Enable
This Read/Write bit-field permits the user to configure
the Receive Section of the Channel to verify (or not
verify) the BIP-4 value within each incoming E3
frame.
Setting this bit-field to "0", configures the Receive
Section of the Channel to NOT verify the BIP-4 value
within each incoming E3 frame.
Setting this bit-field to "1", configures the Receive
Section of the Channel to verify the BIP-4 value within
each incoming E3 frame.
2.4.4.2 Receive E3 Framer Configuration &
Status Register -2 (E3, ITU-T G.751)
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
R/W
RO
RO
RO
RO
RO
RO
0
1
1
0
0
1
1
BIT 0
RxFERF
RO
1
Bit 7 - RxLOF (Receive Loss of Frame) Al-
go(rithm) Select
This Read/Write bit-field permits the user to select
the Receive Loss of Frame Declaration Algorithm, for
the Receive Section of the Channel.
Setting this bit-field to "0" configures the Receive
Section to declare a Loss of Frame condition, if it re-
sides in the OOF (Out of Frame) Condition for 24 E3
Frame periods. Likewise, the Receive Section will
clear the Loss of Frame condition, if it resides in the
In-Frame condition for 24 E3 Frame periods.
Setting this bit-field to "1" configures the Receive
Section to declare a Loss of Frame condition, if it re-
sides in the OOF (Out of Frame) condition for 8 E3
Frame periods. Likewise, the Receive Section will
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