XRT72L56 Datasheet, PDF (187/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
the 11.184MHz clock signal via the
DS3_Nib_Clock_In input pin. The XRT72L56 will out-
put the 11.184MHz clock signal via the TxNibClk out-
put pin.
The Terminal Equipment will serially output the data
on the DS3_Data_Out[3:0] pins upon the rising edge
of the signal at the DS3_Clock_In input pin. The
XRT72L56 will latch the data, residing on the Tx-
Nib[3:0] input pins, on the rising edge of the TxNibClk
signal.
In this case the XRT72L56 has the responsibility of
providing the framing reference signal by pulsing the
TxFrame output pin (and in turn the
Tx_Start_of_Frame input pin of the Terminal Equip-
ment) "High" for one bit-period, coincident with the
last bit within a given DS3 frame.
Finally, the XRT72L56 will always internally generate
the Overhead bits, when it is operating in both the
DS3 and Nibble-parallel modes. The XRT72L56 will
pull the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L56
and the Terminal Equipment for DS3 Mode 6 Opera-
tion is illustrated in Figure 55.
FIGURE 55. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L56 AND THE TERMINAL
EQUIPMENT (DS3 MODE 6 OPERATION)
Terminal Equipment Signals
TxInClk
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
Nibble [1175]
Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [1175]
Nibble [0]
DS3 Frame Number N
DS3 Frame Number N + 1
Note: TxNibFrame pulses high to denote
DS3 Frame Boundary.
Sampling Edge of the XRT72L5x Device
How to configure the XRT72L56 into Mode 6
1. Set the NibInt input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to 1X as illus-
trated below.
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