XRT72L56 Datasheet, PDF (137/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
This Read/Write bit-field permits the user to insert er-
rors into EM (Error Monitor) octet of each outbound
E3 frame. The user may wish to do this for equip-
ment testing purposes. Prior to transmission, the
Transmit DS3/E3 Framer block reads in the EM byte,
and performs an XOR operation with it and the con-
tents of this register. The results of this operation are
written back into the EM octet position, in each out-
bound E3 frame. Consequently, to insure errors are
not injected into the EM octet of the outbound E3
frames, the contents of this register must be set to all
"0’s" (the default value).
2.4.7 Transmit E3 Framer Configuration Regis-
ters (ITU-T G.751)
2.4.7.1 Transmit E3 Configuration Register
(ITU-T G.751)
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Tx
BIP-4
Enable
TxASourceSel[1:0]
TxNSourceSel[1:0]
Tx AIS
Enable
Tx LOS
Enable
Tx FAS
Source
Select
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - TxBIP-4 Enable
This Read/Write bit-field permits the user to configure
the Transmit Section of the Channel, to compute an
insert the BIP-4 value into each outbound E3 frame.
Setting this bit-field to "0", configures the Transmit
Section of the Channel to NOT compute and insert
the BIP-4 value into each outbound E3 frame. In-
stead these four bits will contain data that has been
input via the Input Interface.
Setting this bit-field to "1", configures the Transmit
Section of the Channel to compute and insert the
BIP-4 value into each outbound E3 frame.
NOTE: For more information on these BIP-4 Calculations,
please see Section 4.2.4.2.2.
Bit 6, 5, TxASourceSel[1:0]
These two Read/Write bit-fields combine to specify
the source of the A-bit, within each outbound E3
frame. The relationship between these two bit-fields
and the resulting source of the A Bit is tabulated be-
low.
TXASOURCESEL[1:0]
SOURCE OF A BIT
00
TxE3 Service Bits Register (Address = 0x35)
01
Transmit Overhead Data Input Interface
10
Transmit Payload Data Input Interface
11
Functions as a FEBE (Far-End-Block Error) bit-field.
This bit-field is set to "0", if the Near-End Receive Section (within this chip) detects no BIP-4
Errors within the incoming E3 frames.
This bit-field is set to "1", if the Near-End Receive Section (within this chip) detects a BIP-4
Error within the incoming E3 frame.
NOTE: For more information on the A-bit, within the ITU-T
G.751 frame, please see Section 4.1.1.1.
Bits 4, 3, TxNSourceSel[1:0]
These two Read/Write bit-fields combine to specify
the source of the N-bit, within each outbound E3
frame. The relationship between these two bit-fields
and the resulting source of the N Bit is tabulated be-
low.
TXNSOURCESEL[1:0]
SOURCE OF N BIT
00
TxE3 Service Bits Register (Address = 0x35)
118