XRT72L56 Datasheet, PDF (276/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
Mode 1 Operation of the Terminal Equipment
When the XRT72L56 is operating in this mode, it will
function as the source of the 34.368MHz clock signal.
This clock signal will be used as the Terminal Equip-
ment Interface clock by both the XRT72L56 IC and
the Terminal Equipment.
The Terminal Equipment will serially output the pay-
load data of the outbound E3 data stream via its
E3_Data_Out pin. The Terminal Equipment will up-
date the data on the E3_Data_Out pin upon the rising
edge of the 34.368 MHz clock signal, at its
E3_Clock_In input pin (as depicted in Figure 100 and
Figure 101).
The XRT72L56 will latch the outbound E3 data
stream (from the Terminal Equipment) on the rising
edge of the RxOutClk signal.
The XRT72L56 will indicate that it is processing the
last bit, within a given outbound E3 frame, by pulsing
its TxFrame output pin "High" for one bit-period.
When the Terminal Equipment detects this pulse at its
Tx_Start_of_Frame input, it is expected to begin
transmission of the very next outbound E3 frame to
the XRT72L56 via the E3_Data_Out (or TxSer pin).
Finally, the XRT72L56 will indicate that it is about to
process an overhead bit by pulsing the TxOH_Ind
output pin "High" one bit period prior to its processing
of an OH (Overhead) bit. In Figure 100, the
TxOH_Ind output pin is connected to the
E3_Overhead_Ind input pin of the Terminal Equip-
ment. Whenever the E3_Overhead_Ind pin is pulsed
"High" the Terminal Equipment is expected to not
transmit a E3 payload bit upon the very next clock
edge. Instead, the Terminal Equipment is expected to
delay its transmission of the very next payload bit, by
one clock cycle.
The behavior of the signals, between the XRT72L56
and the Terminal Equipment, for E3 Mode 1 operation
is illustrated in Figure 101.
Inserting the A and N bits into the outbound E3
frames via the Transmit Payload Data Input Inter-
face block
The XRT72L56 DS3/E3 Framer permits the Terminal
Equipment to insert its own values for the “A” and/or
“N” bits, into the outbound E3 frame, via the Transmit
Payload Data Input Interface block. If the user de-
sires to do this, the XRT72L56 Framer IC must be
configured to accept the Terminal Equipment’s value
for the “A” and “N” bits, by writing to appropriate data
into the TxASourceSel[1:0] and TxNSourceSel[1:0]
bit-fields, within the TxE3 Configuration Register (Ad-
dress =0x30), as illustrated below.
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Tx
BIP-4
Enable
TxASourceSel[1:0]
TxNSourceSel[1:0]
Tx AIS
Enable
Tx LOS
Enable
Tx FAS
Source
Select
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
X
X
X
X
0
0
0
Configuring the Transmit Payload Data Input In-
terface block to accept the “A Bits” from the Ter-
minal Equipment
If the user wishes to configure the Transmit Payload
Data Input Interface block to accept the “A” bits from
the Terminal Equipment, then the user must write the
value “10” into the TxASourceSel[1:0] bit-fields.
Once the user does this, then any value, which re-
sides on the TxSer input pin, when the “A” bit is being
processed by the Transmit Section will be inserted in-
to the “A” bit-field within the very next outbound E3
frame.
For completeness, the relationship between the con-
tents of the TxASourceSel[1:0] bits and the resulting
source of the “A” bit is listed below.
Bit 6, 5, TxASourceSel[1:0]
These two Read/Write bit-fields combine to specify
the source of the A-bit, within each outbound E3
frame. The relationship between these two bit-fields
and the resulting source of the A Bit is tabulated be-
low.
TXASOURCESEL[1:0]
SOURCE OF A BIT
00
TxE3 Service Bits Register (Address = 0x35)
257