XRT72L56 Datasheet, PDF (176/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
A. Local-Timing - Uses the TxInClk signal as the
Timing Reference
In this mode, the Transmit Section of the XRT72L56
will use the TxInClk signal as its timing reference.
B. Serial Mode
The XRT72L56 will receive the DS3 payload data, in
a serial manner, via the TxSer input pin. The Trans-
mit Payload Data Input Interface (within the
XRT72L56) will latch this data into its circuitry, on the
rising edge of the TxInClk input clock signal.
C. Delineation of outbound DS3 frames (Frame
Slave Mode)
The Transmit Section (of the XRT72L56) will use the
TxInClk input as its timing reference, and will use the
TxFrameRef input signal as its framing reference. In
other words, the Transmit Section of the XRT72L56
will initiate frame generation upon the rising edge of
the TxFrameRef input signal).
D. Sampling of payload data, from the Terminal
Equipment
In Mode 2, the XRT72L56 will sample the data, at the
TxSer input pin, on the rising edge of TxInClk.
Interfacing the Transmit Payload Data Input Inter-
face block (of the XRT72L56) to the Terminal
Equipment for Mode 2 Operation
Figure 46 presents an illustration of the Transmit Pay-
load Data Input Interface block (within the XRT72L56)
being interfaced to the Terminal Equipment, for Mode
2 operation.
FIGURE 46. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L56 FOR MODE 2 (SERIAL/LOCAL-TIMED/FRAME-SLAVE) OPERATION
44.736 MHz Clock
Source
DS3_Clock_In
DS3_Data_Out
Tx_Start_of_Frame
DS3_Overhead_Ind
TxInClk
TxSer
TxFrameRef
TxOH_Ind
NibInt
Terminal Equipment
XRT72L5x DS3 Framer
Mode 2, Operation of the Terminal Equipment
As shown in Figure 46, both the Terminal Equipment
and the XRT72L56 will be driven by an external
44.736MHz clock signal. The Terminal Equipment
will receive the 44.736MHz clock signal via its
DS3_Clock_In input pin, and the XRT72L56 Framer
IC will receive the 44.736MHz clock signal via the Tx-
InClk input pin.
The Terminal Equipment will serially output the pay-
load data of the outbound DS3 data stream, via the
DS3_Data_Out output pin, upon the rising edge of
the signal at the DS3_Clock_In input pin.
NOTE: The DS3_Data_Out output pin of the Terminal
Equipment is electrically connected to the TxSer input pin.
The XRT72L56 Framer IC will latch the data, residing
on the TxSer input line, on the rising edge of the TxIn-
Clk signal.
In this case, the Terminal Equipment has the respon-
sibility of providing the framing reference signal by
pulsing its Tx_Start_of_Frame output signal (and in
turn, the TxFrameRef input pin of the XRT72L56),
"High" for one-bit period, coincident with the first bit of
a new DS3 frame. Once the XRT72L56 detects the
rising edge of the input at its TxFrameRef input pin, it
will begin generation of a new DS3 frame.
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