XRT72L56 Datasheet, PDF (143/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L56
REV. P1.1.2
This Reset-upon-Read register, along with the PMON
Parity Error Count Register - MSB (Address = 0x54)
contains a 16-bit representation of the number of P-
bit Errors (for DS3 applications), BIP-4 Errors (for E3/
ITU-T G.751 applications) or BIP-8 Errors (for E3/
ITU-T G.832 applications) that have been detected by
the Receive DS3/E3 Framer block, since the last read
of these registers. This register contains the LSB (or
Lower-Byte) value of this 16 bit expression.
2.4.8.7 PMON FEBE Event Count Register -
MSB
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FEBE Event Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
FEBE Event Count Register - LSB (Address = 0x57)
contains a 16-bit representation of the number of
FEBE Events that have been detected by the Receive
DS3/E3 Framer block, since the last read of these
registers. This register contains the MSB (or Upper-
Byte) value of this 16 bit expression.
2.4.8.8 PMON FEBE Event Count Register -
LSB
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FEBE Event Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
FEBE Event Count Register - MSB (Address = 0x56)
contains a 16-bit representation of the number of
FEBE Events that have been detected by the Receive
DS3/E3 Framer block, since the last read of these
registers. This register contains the LSB (or Lower-
Byte) value of this 16 bit expression.
2.4.8.9 PMON CP-Bit Error Event Count Regis-
ter - MSB
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
CP-Bit Error Count Register - LSB (Address = 0x59)
contains a 16-bit representation of the number of CP-
bit Errors that have been detected by the Receive
DS3/E3 Framer block (within the channel), since the
last read of these registers. This register contains the
MSB (or Upper-Byte) value of this 16 bit expression.
NOTE: This register is only active if the Channel has been
configured to operate in the DS3, C-bit Parity Framing for-
mat.
2.4.8.10 PMON CP-Bit Error Event Count Regis-
ter - LSB
124