XRT72L56 Datasheet, PDF (160/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
to the following states: A2 = ‘0’, A1 = ‘0’ and A0 = ‘1’
(which is the number 6 in Highinverted binary format).
The state of three output pins will be read by the ac-
tive-low interrupt request inputs of the Microproces-
sor (IPL2, IPL1, IPL0). When the MC68000 Micro-
processor detects this value at its three interrupt re-
quest inputs, it will know two things.
1. An interrupt request has been issued by one of
the peripheral devices.
2. The interrupt request is a Level 6 interrupt
request (due to the values of the A2 - A0 outputs
from the Interrupt Priority Encoder IC).
Once the MC68000 Microprocessor has determined
these two things it will initiate an Interrupt Acknowl-
edge (IACK) cycle by doing the following:
1. Identify this new bus cycle as an interrupt service
routine by setting all of its Function Code output
pins (FC2 - FC0) to "High”.
2. Placing the interrupt level on the Address output
pins A[3:1].
When the MC68000 Microprocessor has toggled all
of its Function Code output pin "High”, the Function
Code Decoder chip (U3) will read this value from the
FC2 - FC0 pins as being the binary value for 7. As a
result, U3 will assert its active-low Y7 output pin. At
the same time, the address lines A[3:1] are carrying
the current Interrupt Level of this IACK cycle (level =
6, or “110” in this example) and applying this value to
the A, B, and C inputs of the IACK Level Decoder chip
(U5). Initially, all of the outputs of U5 are tri-stated.
Due to the fact that its active-low G2A and G2B inputs
are negated (e.g., at a logic "High”). However, when
the MC68000 Microprocessor begins the IACK cycle,
it will assert its Address Strobe (AS*) signal. This ac-
tion will result in asserting the G2A input pin of U5.
Additionally, since the Function Code Decoder chip
has also asserted its Y7 output pin this will, in turn,
assert the G2A input pin of U5. At this point, the out-
put of U5 will no longer be tri-stated. U5 will read in
the contents of its A, B, and C inputs, and assert the
active-low VPA* (Valid Peripheral Address) input pin
of the MC68000. Anytime the MC68000 detects its
VPA* pin being asserted during an IACK cycle, it
knows that this is an Auto-Vectored Interrupt cycle.
Further, it also knows that it will not receive an inter-
rupt vector from the peripheral device (e.g., the
XRT72L56 DS3/E3 Framer IC, in this case), and that
it must generate its own vector. In the very next bus
cycle, the MC68000 is going to implement a pseudo-
read of the data bus. However, in reality, no data will
be read from the XRT72L56. The MC68000 will in-
stead have determined that since this current IACK
cycle is an Auto-Vectored - Level 6 Interrupt cycle,
which corresponds to Vector Number 30, within the
MC68000’s Exception Vector Table. Vector Number
30 corresponds to an Address Space of 0x78, in the
MC68000’s address space. In the case of this exam-
ple, the user is required to place an unconditional
branch statement (to the location of the XRT72L56 In-
terrupt Service Routine) at 0x78 in system memory.
Table 15 presents the Auto-Vector Table (e.g., the re-
lationship between the Interrupt Level and the corre-
sponding location in memory for this unconditional
branch statement) for the MC68000 Microprocessor.
TABLE 15: AUTO-VECTOR TABLE FOR THE MC68000 MICROPROCESSOR
INTERRUPT
LEVEL
VECTOR NUMBER
ADDRESS LOCATION (OF UNCONDITIONAL BRANCH INSTRUCTION - FOR INTERRUPT
SERVICE ROUTINE)
1
25
0x064
2
26
0x068
3
27
0x06C
4
28
0x070
5
29
0x074
6
30
0x078
7
31
0x07C
3.0 THE LINE INTERFACE AND SCAN SECTION
The Line Interface and Scan Section of the
XRT72L56 DS3/E3 Framer IC consists of 5 output
pins, 3 input pins, a Read/Write register, and a Read-
Only register.
The purpose of the Line Interface Drive and Scan
section is to permit the user to monitor and exercise
control over many aspects of the XRT7300 DS3/E3/
STS-1 LIU IC without having to develop the neces-
sary off-chip glue-logic.
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