XRT72L56 Datasheet, PDF (89/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
2.4.2.2 I/O Control Register
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
Disable
TxLOC
LOC
Disable
RxLOC
AMI/
ZeroSup*
BIT 3
Unipolar/
Bipolar*
R/W
RO
R/W
R/W
R/W
1
0
1
0
0
BIT 2
TxLine
Clk
Invert
R/W
0
BIT 1
RxLine
Clk
Invert
R/W
0
XRT72L56
REV. P1.1.2
BIT 0
Reframe
R/W
0
Bit 7 - DisableTxLOC
This Read/Write bit-field permits the user to enable or
disable the Transmit Loss of Clock feature.
Setting this bit-field to "0" enables the Transmit Loss
of Clock feature. Conversely, setting this bit-field to
"1" disables the Transmit Loss of Clock feature.
NOTE: For more details into the Transmit Loss of Clock fea-
ture, please see Section 1.4.
Bit 6 - LOC (Loss of Clock) Status
This Read-Only bit-field reflects the Loss of Clock
status for the XRT72L56. The XRT72L56 will set this
bit-field to "0" under normal operation conditions.
Conversely, if the XRT72L56 has experiences a Loss
of Clock event, then it will set this bit-field to "1".
NOTE: For more details into the Loss of Clock status,
please see Section 1.4.
Bit 5 - DisableRxLOC
This Read/Write bit-field permits the user to enable or
disable the Receive Loss of Clock feature.
Setting this bit-field to "0" enables the Receive Loss
of Clock feature. Conversely, setting this bit-field to
"1" disables the Receive Loss of Clock feature.
NOTE: For more details into the Receive Loss of Clock fea-
ture, please see Section 1.4.
Bit 4 - AMI/ZeroSup*
This Read/Write bit-field permits the user to configure
the XRT72L56 to transmit and receive data via the
AMI (Alternate Mark Inversion) line code or via a Ze-
ro-Suppression (e.g, B3ZS/HDB3) line code.
Setting this bit-field to "0" configures the XRT72L56 to
transmit and receive data via a Zero-Suppression line
code.
Setting this bit-field to "1" configures the XRT72L56 to
transmit and receive data via the Alternate Mark In-
version line code.
NOTES:
1. If the XRT72L56 is configured to transmit and
receive data, using a Zero-Suppression code, while
operating in the DS3 Mode, then the chip will trans-
mit and receive data using the B3ZS Line Code.
2. If the XRT72L56 is configured to transmit and
receive data, using a Zero-Suppression code, while
operating in the E3 Mode, then the chip will trans-
mit and receive data using the HDB3 Line Code.
3. This bit-field will be ignored if bit 3 (Unipolar/Bipo-
lar*) of this Register is set to "1" (for Unipolar
Mode).
Bit 3 - Unipolar/Bipolar*
This Read/Write bit-field permits the user to configure
the XRT72L56 to transmit data to and receive data
from an LIU IC, in either the Single-Rail or Dual-Rail
format.
Setting this bit-field to "0" configures the XRT72L56 to
operate in the Bipolar or Dual-Rail Format. In this
mode, the Transmit Section of the XRT72L56 will out-
put data to the LIU via both the TxPOS and TxNEG
output pins. Additionally, the Receive Section of the
device will receive data from the LIU via both the Rx-
POS and RxNEG output pins.
Setting this bit-field to "1" configures the XRT72L56 to
operate in the Unipolar or Single-Rail Format. In this
mode, the Transmit Section of the XRT72L56 will out-
put data to the LIU, in a binary data stream manner
via the TxPOS output pin. Additionally, the Receive
Section of the device will receive data from the LIU, in
a binary data stream manner, via the RxPOS input
pin.
NOTE: For more information on the transmission and
reception of data in the Single-Rail or Dual-Rail format,
please see Section 3.2.5.
Bit 2 - TxLineClk Invert
This Read/Write bit-field permits the user to configure
the XRT72L56 to output data, via the TxPOS and Tx-
NEG output pins, on the rising or falling edge of TxLi-
neClk.
Setting this bit-field to "0" configures the XRT72L56 to
output data, via the TxPOS and TxNEG output pins,
on the rising edge of TxLineClk.
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