XRT72L56 Datasheet, PDF (186/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
TxNibClk signal, to latch the data, residing on the Tx-
Nib[3:0] into its circuitry.
B. Nibble-Parallel Mode
The XRT72L56 will accept the DS3 payload data,
from the Terminal Equipment, in a parallel manner,
via the TxNib[3:0] input pins. The Transmit Terminal
Equipment Input Interface will latch this data into its
circuitry, on the rising edge of the TxNibClk output
signal.
C. Delineation of outbound DS3 Frames
The Transmit Section will use the TxInClk input signal
as its timing reference and will initiate the generation
of DS3 frames, asynchronous with respect to any ex-
ternal signal. The XRT72L56 will pulse the TxFrame
output pin "High" whenever it is processing the last
nibble, within a given outbound DS3 frame.
D. Sampling of payload data, from the Terminal
Equipment
In Mode 6, the XRT72L56 will sample the data, at the
TxNib[3:0] input pins, on the third rising edge of the
TxInClk clock signal, following a pulse in the TxNibClk
signal (see Figure 55).
NOTE: The TxNibClk signal from the XRT72L56, operates
nominally at 11.184 MHz (e.g., 44.736 MHz divided by 4).
However, for reasons described below, TxNibClk effectively
operates at a "Low"er clock frequency. The Transmit Pay-
load Data Input Interface is only used to accept the payload
data, which is intended to be carried by outbound DS3
frames. The Transmit Payload Data Input Interface is not
designed to accommodate the entire DS3 data stream.
The DS3 Frame consists of 4704 payload bits or 1176
nibbles. Therefore, the XRT72L56 will supply 1176
TxNibClk pulses between the rising edges of two con-
secutive TxNibFrame pulses. The DS3 Frame repeti-
tion rate is 9.398kHz. Hence, 1176 TxNibClk pulses
for each DS3 frame period amounts to TxNibClk run-
ning at approximately 11.052 MHz. The method by
which the 1176 TxNibClk pulses are distributed
throughout the DS3 frame period is presented below.
Nominally, the Transmit Section within the XRT72L56
will generate a TxNibClk pulse for every 4 RxOutClk
(or TxInClk) periods. However, in 14 cases (within a
DS3 frame period), the Transmit Payload Data Input
Interface will allow 5 TxInClk periods to occur be-
tween two consecutive TxNibClk pulses.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT72L56 to the Terminal Equip-
ment for Mode 6 Operation
Figure 54 presents an illustration of the Transmit Pay-
load Data Input Interface block (within the XRT72L56)
being interfaced to the Terminal Equipment, for Mode
6 Operation.
FIGURE 54. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L56 FOR MODE 6 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-MASTER)
OPERATION
44.736MHz Clock Source
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
11.184MHz
4
VCC
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
NibInt
Terminal Equipment
XRT72L5x DS3 Framer
Mode 6 Operation of the Terminal Equipment
In Figure 54 both the Terminal Equipment and the
XRT72L56 will be driven by an external 11.184MHz
clock signal. The Teriminal Equipment will receive
167