XRT72L56 Datasheet, PDF (320/486 Pages) Exar Corporation – SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
• Receive HDLC Controller block
• Receive E3 Framer block
• Receive Overhead Data Output Interface block
• Receive Payload Data Output Interface block
Figure 127 presents a simple illustration of the Re-
ceive Section of the XRT72L56 Framer IC.
FIGURE 127. A SIMPLE ILLUSTRATION OF THE RECEIVE SECTION OF THE XRT72L56 CONFIGURED TO OPERATE IN
THE E3 MODE
RxOHFrame
RxOHEnable
RxOH
RxOHClk
RxOHInd
RxSer
RxNib[3:0]
RxClk
RxFrame
Receive Overhead
Input
Interface Block
Receive
Payload Data
Input
Interface Block
Receive DS3/E3
Framer Block
Receive LIU
Interface
Block
RxPOS
RxNEG
RxLineClk
From Microprocessor
Interface Block
RRxxEE33HHDDLLCC
CConontrtorlollelre/rB/Buufffefrer
Each of these functional blocks will be discussed in
detail in this document.
5.3.1 The Receive E3 LIU Interface Block
The purpose of the Receive E3 LIU Interface block is
two-fold:
1. To receive encoded digital data from the E3 LIU
IC.
2. To decode this data, convert it into a binary data
stream and to route this data to the Receive E3
Framer block.
Figure 128 presents a simple illustration of the Re-
ceive E3 LIU Interface block.
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